参数资料
型号: M37221M8H-XXXSP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP42
封装: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件页数: 68/112页
文件大小: 1179K
代理商: M37221M8H-XXXSP
M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00
Oct 01, 2002
page 59 of 110
REJ03B0134-0100Z
The vertical display start position is determined by counting the hori-
zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are
positive polarity (negative polarity), the count starts at the rising edge
(falling edge) of HSYNC signal after the fixed cycle of the rising edge
(falling edge) of VSYNC signal. So the interval from the rising edge
(falling edge) of VSYNC signal to the rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) to avoid jitters.
The polarity of HSYNC and VSYNC signals can be select with the OSD
port control register (address 00EC16).
Fig. 8.11.5 Supplement Explanation for Display Position
When bits 0 and 1 of the OSD port control register
(address 00EC16) are set to “1” (negative polarity)
VSYNC signal input
VSYNC control
signal in
microcomputer
0.125 to 0.25 [s]
( at f(XIN) = 8MHz)
Period of counting
HSYNC signal
(See note 2)
HSYNC
signal input
Not count
12345
Notes 1 : The vertical position is determined by counting falling edge of HSYNC
signal after rising edge of VSYNC control signal in the microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge of
VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or
more.
8 machine cycles
or more
8 machine cycles
or more
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