参数资料
型号: M37221MAH-XXXFP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42
封装: 0.450 INCH, 0.80 MM INCH, PLASTIC, SSOP-42
文件页数: 46/112页
文件大小: 1207K
代理商: M37221MAH-XXXFP
39
Rev. 1.0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
M37221M4H/M6H/M8H/MAH–XXXSP/FP
M37221EASP/FP
MITSUBISHI MICROCOMPUTERS
8.6.6 START Condition Generation Method
When the ESO bit of the I2C control register (address 00DA16) is “1,”
execute a write instruction to the I2C status register (address 00D916)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
is output for 1 byte . The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 8.6.9 for the START condition
generation timing diagram, and Table 8.6.2 for the START condition/
STOP condition generation timing table.
Fig. 8.6.9 START Condition Generation Timing Diagram
I2C statusregiste
write signal
Set time for
BB flag
Hold time
Setup
time
SCL
SDA
BB flag
Setup
time
8.6.7 STOP Condition Generation Method
When the ESO bit of the I2C control register (address 00DA16) is “1,”
execute a write instruction to the I2C status register (address 00D916)
to set the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP
condition will then be generated. The STOP condition generation tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 8.6.10 for the
STOP condition generation timing diagram, and Table 8.6.2 for the
START condition/STOP condition generation timing table.
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Setup time
(START condition)
Setup time
(STOP condition)
Hold time
Set/reset time
for BB flag
Standard Clock Mode
5.0
s (20 cycles)
4.25
s (17 cycles)
5.0
s (20 cycles)
3.0
s (12 cycles)
High-speed Clock Mode
2.5
s (10 cycles)
1.75
s (7 cycles)
2.5
s (10 cycles)
1.5
s (6 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
I2Cstatus register
write signal
Hold time
Setup
time
SCL
SDA
BB flag
Reset time for
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