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参数资料
| 型号： | M37225ECSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42 |
| 文件页数： | 88/127页 |
| 文件大小： | 1897K |
| 代理商： | M37225ECSP |
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62
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
M37225M6/M8/MA/MC–XXXSP
M37225ECSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
The vertical display start position is determined by counting the hori-
zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are
positive polarity (negative polarity), it starts to count the rising edge
(falling edge) of HSYNC signal from after fixed cycle of rising edge
(falling edge) of VSYNC signal. So interval from rising edge (falling
edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal
needs enough time (2 machine cycles or more) for avoiding jitter.
The polarity of HSYNC and VSYNC signals can select with the OSD I/
O polarity register (address 00EB16).
Fig. 8.10.10 Supplement Explanation for Display Position
When bits 0 and 1 of the I/O polarity control register
(address 00EB16) are set to “1” (negative polarity)
VSYNC signal input
VSYNC control
signal in
microcomputer
0.25 to 0.50 [
s]
( at f(XIN) = 8MHz)
(See note 2)
Not count
123
45
Notes 1 : The vertical position is determined by counting falling edge of
HSYNC signal after rising edge of VSYNC control signal in the
microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles
or more.
8 machine cycles or more
8 machine cycles
or more
HSYNC
signal input
Period of counting
HSYNC signal
Fig. 8.10.11 Block i V Register (i = 1, 2)
The vertical display start position for each block can be set in 255
steps (where each step is 1H (H: HSYNC cycle)) as values “0116” to
“FF16” in block i V register (i = 1, 2) (addresses 00E116 to 00E216).
When setting the block i V register to “0116,” the display is started at
18H of count value of HSYNC signal. The vertical display start posi-
tion here indicates the top position of character display area in OSD/
BUTTON mode.
The block i V register is shown in Figures 8.10.11.
b7b6b5b4b3b2b1b0
Block i V register (BiVP) (i = 1, 2) [Addresses 00E116 and 00E216]
BNameFunctions
After reset R W
Block i V Register
0
to
7
Control bits of
vertical display
start positions
(BiVP0 to BiVP7)
(See note 1)
Indeterminate RW
Note: Set values except “0016” to BiVP.
Vertical display start positions = Hdef + H n
(n: setting value, Hdef: 17H, H: HSYNC)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M37225M6 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER |
| M37225M8 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER |
| M37225MA | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER |
| M372429100 | 制造商:ITW Switches 功能描述:IN-RUSH |
| M372429200 | 制造商:ITW Switches 功能描述:IN-RUSH |
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