参数资料
型号: M37272MFH-XXXSP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP42
封装: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件页数: 68/131页
文件大小: 1297K
代理商: M37272MFH-XXXSP
41
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH–XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
(3) RESTART condition generating procedure
Procedure example (The necessary conditions of the generating
procedure are described as the following to .)
Execute the following procedure when the PIN bit is “0.”
LDM
#$00, S1
(Select slave receive mode)
LDA
(Taking out of slave address value)
SEI
(Interrupt disabled)
STA
S0
(Writing of slave address value)
LDM
#$F0, S1
(Trigger of RESTART condition generating)
CLI
(Interrupt enabled)
Select the slave receive mode when the PIN bit is “0.” Do not write
“1” to the PIN bit. Neither “0” nor “1” is specified for the writing to
the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
The SCL pin is released by writing the slave address value to the
I2C data shift register. Use “STA,” “STX” or “STY” of the zero page
addressing instruction for writing.
Use “LDM” instruction for setting trigger of RESTART condition gen-
erating.
Write the slave address value of above and set trigger of RE-
START condition generating of above continuously shown the
above procedure example.
Disable interrupts during the following two process steps:
Writing of slave address value
Trigger of RESTART condition generating
(4) STOP condition generating procedure
Procedure example (The necessary conditions of the generating
procedure are described as the following to .)
SEI
(Interrupt disabled)
LDM #$C0, S1
(Select master transmit mode)
NOP
(Set NOP)
LDM #$D0, S1
(Trigger of STOP condition generating)
CLI
(Interrupt enabled)
Write “0” to the PIN bit when master transmit mode is select.
Execute “NOP” instruction after setting of master transmit mode.
Also, set trigger of STOP condition generating within 10 cycles af-
ter selecting of master trasmit mode.
Disable interrupts during the following two process steps:
Select of master transmit mode
Trigger of STOP condition generating
(5) Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an
instruction to set the MST and TRX bits to “0” from “1” simultaneously.
It is because it may enter the state that the SCL pin is released and
the SDA pin is released after about one machine cycle. Do not ex-
ecute an instruction to set the MST and TRX bits to “0” from “1” si-
multaneously when the PIN bit is “1.” It is because it may become the
same as above.
(6) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I2C status
register S1 until the bus busy flag BB becomes “0” after generating
the STOP condition in the master mode. It is because the STOP
condition waveform might not be normally generated. Reading to the
above registers do not have the problem.
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