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| 型号： | M3727GM8-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42 |
| 封装： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件页数： | 77/129页 |
| 文件大小： | 1211K |
| 代理商： | M3727GM8-XXXFP |
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51
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M3727GM6/M8–XXXSP/FP
M37272E8SP/FP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
8.10.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video
signal input from the CVIN pin. The low-pass filter attenuates the noise
of clamped composite video signal. The CVIN pin to which composite
video signal is input requires a capacitor (0.1
F) coupling outside.
Pull down the CVIN pin with a resistor of hundreds of kiloohms to 1
M
. In addition, we recommend to install externally a simple low-
pass filter using a resistor and a capacitor at the CVIN pin (refer to
Figure 8.10.1).
8.10.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter.
8.10.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
(1)Horizontal Synchronous Signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
(2)Vertical Synchronous Signal (Vsep)
As a Vsep signal generating method, it is possible to select one of
the following 2 methods by using bit 4 of the data slicer control
register 2 (address 00E116).
Method 1
The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, a Vsep
signal is generated in synchronization with the rising
of the timing signal immediately after this LOW level.
Method 2
The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync sig-
nal exits or not in the LOW level period of the timing
signal immediately after this LOW level. If a falling
exists, a Vsep signal is generated in synchronization
with the rising of the timing signal (refer to Figure
8.10.6).
Figure 8.10.6 shows a Vsep generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 8.10.7, when the A level matches the B level, this bit
is “0.” In the case of a mismatch, the bit is “1.”
Fig. 8.10.6 Vsep Generating Timing (method 2)
Composite s
Timing
signal
Vsep signal
Measure LOW period
A Vsep signal is generated at a rising of the timing signal
immediately after the LOW level width of the composite
sync signal exceeds a certain time.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M3727GM8-XXXSP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37280EKSP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37280EKSS | 功能描述:EPROM MCU/8BIT CMOS EMULATION CH RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| M37280MF | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37280MF_03 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
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