7531 Group User’s Manual
APPLICATION
2-53
2.4 A-D converter
Fig. 2.4.5 Structure of Interrupt edge selection register
Fig. 2.4.6 Structure of Interrupt request register 1
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset
RW
0
1
2
3
4
5
6
7
Name
0
Interrupt request register 1 (IREQ1) [Address : 3C 16]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
!
Serial I/O1 receive
interrupt request bit
Serial I/O1 transmit or INT 1
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
Timer 2 or serial I/O2 interrupt
request bit
CNTR0 or AD converter
interrupt request bit
V: These bits can be cleared to “0” by program, but cannot be set to “1”.
0 : No interrupt request issued
1 : Interrupt request issued
INT0 interrupt request bit
Timer X or key-on wake up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
V
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset
RW
0
1
2
3
4
5
6
7
Name
0
Interrupt edge selection register (INTEDGE) [Address : 3A 16]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
!
INT0 interrupt edge
selection bit
INT1 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
Serial I/O1 or INT 1 interrupt
selection bit (Note)
Timer X or key-on wake up
interrupt selection bit
Timer 2 or serial I/O2 interrupt
selection bit
CNTR0 or AD converter
interrupt selection bit
0 : Serial I/O1
1 : INT1
0 : Timer X
1 : Key-on wake up
0 : Timer 2
1 : Serial I/O2
0 : CNTR0
1 : AD converter
Note: Do not write “1” to bit 4 in the 32-pin package versions.