7531 Group User’s Manual
2-50
APPLICATION
2.3 Serial I/O
2.3.6 Notes on serial I/O
(1) Handling of clear the serial I/O1
When serial I/O1 is set again or the transmit/receive operation is stopped/restarted while serial I/O1
is operating, clear the serial I/O1 as shown in Figure 2.3.28.
Fig. 2.3.28 Sequence of clearing serial I/O
→Set again (Note)
○○
Serial I/O1 enabled
Serial I/O1 cleared
Serial I/O1 disabled
Serial I/O1 register set again
Serial I/O1 enabled
Handling of clear the serial I/O1
Note: When the contents of register is not changed, setting again is not necessary.
SIO1CON (address 1A16) bit 7, bit 6
← 102
SIO1CON (address 1A16) bit 7, bit 6
← 112
SIO1CON (address 1A16) bit 7, bit 6
← 002
UARTCON (address 1B16)
BRG (address 1C16)
SIO1CON (address 1A16)
← 10!!!!!!2
Set again (Note)
(2) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(3) Writing transmit data
When an external clock is used as the synchronous clock for the clock synchronous serial I/O, write
the transmit data to the transmit buffer register (serial I/O shift register) at “H” of the transfer clock
input level.
(4) Serial I/O2 transmit/receive shift completion flag
The transmit/receive shift completion flag of the serial I/O2 control register is set to “1” after completing
transmit/receive shift. In order to set this flag to “0”, write data (dummy data at reception) to the
serial I/O2 register by program.
Bit 7 of the serial I/O2 control register is set to “1” a half cycle (of the shift clock) earlier than
completion of shift operation. Accordingly, when using this bit to confirm shift completion, a half
cycle or more of the shift clock must pass after confirming that this bit is set to “1”, before performing
read/write to the serial I/O2 register.