参数资料
型号: M37547G2FP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO36
封装: 8.40 X 15 MM, 0.80 MM PITCH, PLASTIC, SSOP-36
文件页数: 66/97页
文件大小: 1064K
代理商: M37547G2FP
REJ03B0156-0122
Rev.1.22
Mar 31, 2009
page 69 of 94
7547 Group
NOTES ON USE
Countermeasures against noise
1. Shortest wiring length
(1) Package
Select the smallest possible package to make the total wiring
length short.
<Reason>
The wiring length depends on a microcomputer package. Use of a
small package, for example QFP and not DIP, makes the total wir-
ing length short to reduce influence of noise.
(3) Wiring for clock input/output pins
Make the length of wiring which is connected to clock I/O pins as
short as possible.
Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
Separate the VSS pattern only for oscillation from other VSS pat-
terns.
<Reason>
If noise enters clock I/O pins, clock waveforms may be deformed.
This may cause a program failure or program runaway. Also, if a
potential difference is caused by the noise between the VSS level
of a microcomputer and the VSS level of an oscillator, the correct
clock will not be input in the microcomputer.
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as
short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20 mm).
<Reason>
The width of a pulse input into the RESET pin is determined by the
timing necessary conditions. If noise having a shorter pulse width
than the standard is input to the RESET pin, the reset is released
before the internal state of the microcomputer is completely initial-
ized. This may cause a program runaway.
Fig. 90 Wiring for clock I/O pins
Fig. 88 Selection of packages
DIP
SDIP
SOP
QFP
Fig. 89 Wiring for the RESET pin
RESET
Reset
circuit
Noise
VSS
Reset
circuit
VSS
RESET
VSS
N.G.
O.K.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
N.G.
O.K.
(4) Wiring to CNVSS pin
Connect CNVSS pin to a GND pattern at the shortest distance.
The GND pattern is required to be as close as possible to the
GND supplied to VSS.
In order to improve the noise reduction, to connect a 5 k resistor
serially to the CNVSS pin - GND line may be valid.
As well as the above-mentioned, in this case, connect to a GND
pattern at the shortest distance. The GND pattern is required to be
as close as possible to the GND supplied to VSS.
<Reason>
The CNVSS pin of the QzROM is the power source input pin for
the built-in QzROM. When programming in the built-in QzROM,
the impedance of the CNVSS pin is low to allow the electric current
for writing flow into the QzROM. Because of this, noise can enter
easily. If noise enters the CNVSS pin, abnormal instruction codes
or data are read from the built-in QzROM, which may cause a pro-
gram runaway.
Fig. 91 Wiring for the CNVSS pin of the QzPROM
About 5k
VSS
The shortest
CNVSS
(Note)
Note: This indicates pin.
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