参数资料
型号: M37640E8FP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件页数: 26/96页
文件大小: 1477K
代理商: M37640E8FP
32
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pulse Output Mode
Count Source:
F/n (where n is 8, 16, 32, or 64) or
SCSGCLK
Each time the timer X underflows, the output of the
CNTR0 pin is inverted, and the corresponding Timer
X interrupt request bit is set to a “1”. The repeated
inversion of the CNTR0 pin output produces a rect-
angular waveform with a duty ratio of 50 percent. The
initial level of the output is determined by the CNTR0
polarity select bit (bit 6). When this bit is low, the out-
put starts from a high level. When this bit is high, the
output starts from a low level.
Event Counter Mode
Count Source: CNTR0
Timer countdown is triggered by inputs to the CNTR0
pin. Each time a timer underflows, the corresponding
timer interrupt request bit is set to a “1”, the contents
of the timer reload latch are loaded into the timer,
and the countdown sequence begins again.
The edge used to clock Timer X is determined by the
CNTR0 polarity select bit (bit 6).
Pulse Width Measurement Mode
Count Source:
F/n (where n is 8, 16, 32, or 64) or
SCSGCLK
This mode measures either the high or low-pulse
width of the signal on the CNTR0 pin. The pulse width
measured is determined by the CNTR0 polarity se-
lect bit (bit 6). When this bit is “0”, the high pulse is
measured. When this bit is “1”, the low pulse is mea-
sured.
The timer counts down while the level on the CNTR0
pin is the polarity selected by the CNTR0 polarity se-
lect bit. When the timer underflows, the Timer X in-
terrupt request bit is set to a “1”, the contents of the
timer reload latch are reloaded into the timer, and the
timer continues counting down. Each time the signal
polarity switches to the inactive state, a CNTR0 in-
terrupt occurs indicating that the pulse width has been
measured. The width of the measured pulse can be
found by reading Timer X during the CNTR0 inter-
rupt service routine.
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