
POWER SAVING FUNCTIONS
7902 Group User’s Manual
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17.1.2 Particular function select register 1
Figure 17.1.3 shows the structure of the particular function select register 1.
Fig. 17.1.3 Structure of particular function select register 1
(1) Standby state select bit (bit 2)
Setting this bit to “1” allows the I/O pins of the external bus and bus control signals to be switched
to the programmable I/O port pins in the stop and wait modes. (Refer to section “17.2 Bus fixation
in stop and wait modes.”)
(2) Internal clock stop select bit at WIT (bit 3)
Setting this bit to “1” stops operating clocks for the internal peripheral devices and fsys in the wait
mode. (Refer to section “17.3 Stop of system clock in wait mode.”)
RW
(Note 2)
RW
(Note 2)
RW
—
RW
—
Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset.
2: Even when “1” is written, the bit status will not change.
3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is termi-
nated, this bit must be cleared to “0” immediately.
(Note 1)
0
Particular function select register 1 (Address 6316)
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
Function
At reset
R/W
STP-instruction-execution
status bit
WIT-instruction-execution
status bit
Standby state select bit
System clock stop select bit
at WIT
(Note 3)
Address output select bit
The value is “0” at reading.
Timer B2 clock source select bit
(Valid in event counter mode.)
The value is “0” at reading.
0 : Address output changes at access to the inter-
nal area and external area.
1 : Address output changes only at access to the
external area.
0 : Normal operation.
1 : STP instruction has been executed.
0 : Normal operation.
1 : WIT instruction has been executed.
0 : External signal input to the TB2IN pin is counted.
1 : fX32 is counted.
0 : External bus
1 : Programmable I/O port
0 : In the wait mode, system clock fsys is active.
1 : In the wait mode, system clock fsys is stopped.
17.1 Overview