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参数资料
| 型号： | M38049FFHKP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 104/118页 |
| 文件大小： | 1202K |
| 代理商： | M38049FFHKP |
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Rev.1.01
Jan 25, 2005
page 84 of 114
REJ03B0131-0101Z
3804 Group (Spec. H)
q Software Commands
Table 15 lists the software commands.
After setting the CPU rewrite mode select bit to
“
1”, execute a soft-
ware command to specify an erase or program operation.
Each software command is explained below.
Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input
in one of the bus cycles that follow, the contents of the specified
address are read out at the data bus (D0 to D7).
The read array mode is retained until another command is written.
Read Status Register Command (7016)
When the command code
“
7016” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D0
to D7) by a read in the second bus cycle.
The status register is explained in the next section.
Clear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code
“
5016” in the first bus cycle.
Program Command (4016)
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed by
_____
read status register or the RY/BY status flag. When the program
starts, the read status register mode is entered automatically and
the contents of the status register is read at the data bus (D0 to
D7). The status register bit 7 (SR7) is set to “0” at the same time
the write operation starts and is returned to “1” upon completion of
the write operation. In this case, the read status register mode re-
mains active until the read array command (FF16) is written.
Table 15 List of software commands (CPU rewrite mode)
The RY/BY status flag of the flash memory control register is “0”
during write operation and
“
1” when the write operation is com-
pleted as is the status register bit 7.
At program end, program results can be checked by reading the
status register.
Fig. 82 Program flowchart
Command
Program
Clear status register
Read array
Read status register
X
First bus cycleSecond bus cycle
FF16
7016
5016
4016
Write
XSRD
Read
Write
(Note 1)
WA (Note 2)
WD (Note 2)
Block erase
2016
Write
D016
WriteBA (Note 3)
ModeAddress
Data
(D0 to D7)
(Note 4)
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area.
Cycle number
1
2
1
2
X
Data
Start
Write “4016”
Read status register
Program
completed
NO
YES
Write address
Write data
SR4 =
“
0”?
Program
error
NO
YES
SR7 = “1”?
or
RY/BY = “1” ?
Write
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