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参数资料
| 型号： | M38073M4-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件页数： | 9/75页 |
| 文件大小： | 1279K |
| 代理商： | M38073M4-XXXFP |
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16
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts occur by twenty sources: eight external, eleven internal,
and one software.
(1) Interrupt Control
Each interrupt except the BRK instruction interrupt have both an
interrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs if the corresponding
interrupt request and enable bits are "1" and the interrupt disable flag
is "0". Interrupt enable bits can be set or cleared by software. Inter-
rupt request bits can be cleared by software, but cannot be set by
software. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occurs
at the same time the interrupt with highest priority is accepted first.
(2) Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack
3. Concurrently with the push operation, the interrupt jump desti-
nation address is read from the vector table into the program
counter.
4. The interrupt disable flag is set and the corresponding inter-
rupt request bit is cleared.
sNotes on Use
When the active edge of an external interrupt (INT0—INT4, CNTR0
or CNTR1) is set or the timer /INT interrupt source and the ADT/ A-D
conversion interrupt source are changed, the corresponding
interrupt request bit may also be set. Therefore, please take follow-
ing sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(in case of CNTR0: Timer X mode register ; in case of CNTR1:
Timer Y mode register).
(3) Clear the set interrupt request bit to "0."
(4) Enable the external interrupt which is selected.
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