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参数资料
| 型号： | M38227MCA-XXXHP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 11/59页 |
| 文件大小： | 900K |
| 代理商： | M38227MCA-XXXHP |
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Rev.1.20
Dec 24, 2003
page 19 of 57
3822 Group (A ver.)
INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight inter-
nal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software
interrupt set by the BRK instruction. An interrupt occurs if the cor-
responding interrupt request and enable bits are “1” and the
interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
■Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Timer Y mode register (address 2816)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 3416)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit or the interrupt source select bit.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 7 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O data
reception
At completion of serial I/O trans-
mit shift or when transmission
buffer is empty
Interrupt Source
Low
High
Priority
Vector Addresses (Note 1)
Reset (Note 2)
INT0
INT1
Serial I/O
reception
Serial I/O
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR0
CNTR1
Timer 1
INT2
INT3
Key input
(Key-on wake-up)
ADT
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(Valid at falling)
Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
Valid when A-D interrupt is se-
lected
Non-maskable software interrupt
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相关代理商/技术参数 |
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| M38234G4FP#U0 | 功能描述:MCU 2/5V 16K 80-QFP QZ-ROM RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 标准包装:250 系列:80C 核心处理器:8051 芯体尺寸:8-位 速度:16MHz 连通性:EBI/EMI，I²C，UART/USART 外围设备:POR，PWM，WDT 输入/输出数:40 程序存储器容量:- 程序存储器类型:ROMless EEPROM 大小:- RAM 容量:256 x 8 电压 - 电源 (Vcc/Vdd):4.5 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-LCC（J 形引线） 包装:带卷 (TR) |
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