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参数资料
| 型号： | M38227MCA-XXXHP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 24/59页 |
| 文件大小： | 900K |
| 代理商： | M38227MCA-XXXHP |
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Rev.1.20
Dec 24, 2003
page 30 of 57
3822 Group (A ver.)
A-D CONVERTER
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the
A-D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
AN0, and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500 kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock
φ.
Fig. 28 A-D converter block diagram
Fig. 27 Structure of A-D control register
A-D control register
(ADCON : address 003416)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Analog input pin selection bits
0 0 0 : P60/AN0
0 0 1 : P61/AN1
0 1 0 : P62/AN2
0 1 1 : P63/AN3
1 0 0 : P64/AN4
1 0 1 : P65/AN5
1 1 0 : P66/AN6
1 1 1 : P67/AN7
VREF input switch bit
0 : ON during conversion
1 : Always ON
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
b7
b0
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
Comparator
A-D control circuit
ADT/A-D interrupt request
AVSS
VREF
P60/AN0
Data bus
A-D control register
b7
b0
A-D conversion
register
Resistor ladder
C
h
a
n
e
l
s
e
le
c
to
r
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P57/ADT
8
3
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