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参数资料
型号： M38234G4-XXXHP
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封装： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件页数： 18/64页
文件大小： 922K
代理商： M38234G4-XXXHP
Rev.2.02
Jun 19, 2007
page 23 of 73
REJ03B0146-0202
3823 Group
INTERRUPTS
The 3823 group interrupts are vector interrupts with a fixed prior-
ity scheme, and generated by 16 sources among 17 sources: 8
external, 8 internal, and 1 software.
The interrupt sources, vector addresses (1) , and interrupt priority
are shown in Table 9.
Each interrupt except the BRK instruction interrupt has the inter-
rupt request bit and the interrupt enable bit. These bits and the
interrupt disable flag (I flag) control the acceptance of interrupt re-
quests. Figure 16 shows an interrupt control diagram.
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 9 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial interface
data reception
At completion of serial interface
transmit shift or when transmis-
sion buffer is empty
Interrupt Source
Low
High
Priority
Vector Addresses (Note 1)
Reset (Note 2)
INT0
INT1
Serial I/O
reception
Serial I/O
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR0
CNTR1
Timer 1
INT2
INT3
Key input
(Key-on wake-up)
ADT
A/D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
At completion of A/D conversion
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial interface is se-
lected
Valid when serial interface is se-
lected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(Valid at falling)
Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
Valid when A/D interrupt is se-
lected
Non-maskable software interrupt
An interrupt requests is accepted when all of the following
conditions are satisfied:
Interrupt disable flag.................................“0”
Interrupt disable request bit ..................... “1”
Interrupt enable bit................................... “1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
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