
3850 Group (Spec. H) User’s Manual
3-64
APPENDIX
3.5 List of registers
Fig. 3.5.29 Structure of Interrupt control register 1
Fig. 3.5.28 Structure of Interrupt request register 2
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
0
1
2
3
4
5
6
7
Name
0
Functions
At reset R W
0
Timer 1 interrupt
request bit
Timer 2 interrupt
request bit
Serial I/O1 transmit
interrupt request bit
CNTR0 interrupt
request bit
CNTR1 interrupt
request bit
A-D converter
interrupt request bit
Serial I/O1 receive
interrupt request bit
0
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
: “0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
0
1
2
3
4
5
6
7
Name
0
Functions
At reset R W
0
INT0 interrupt
enable bit
Fix this bit to “0”.
INT2 interrupt
enable bit
INT3/Serial I/O2
interrupt enable bit
Timer X interrupt
enable bit
INT1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
Fix this bit to “0”.