
3850 Group (Spec. H) User’s Manual
3-65
APPENDIX
3.5 List of registers
Fig. 3.5.30 Structure of Interrupt control register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
(ICON2 : address 3F16)
b
0
1
2
4
Name
0
Functions
At reset R W
0
Timer 2 interrupt
enable bit
Serial I/O1 transmit
interrupt enable bit
CNTR0 interrupt
enable bit
Serial I/O1 receive
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
5
0
CNTR1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
0
A-D converter
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
Timer 1 interrupt
enable bit
Fix this bit to “0”.
3
Fig. 3.5.31 Structure of Flash memory control register
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16)
b
0
1
2
4
Name
Functions
At reset R W
0
User area/Boot
area selection bit
CPU rewrite mode
select bit (Note 1)
0 : Busy (being written or
erased)
1 : Ready
5
6
7
0
Undefined
RY/BY status flag
Nothing is arranged for these bits. When write,
set “0”. When these bits are read out, the
contents are undefined.
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then
a “1” to it in succession.
2: Effective only when the CPU rewrite mode select bit = “1”. Set this
bit to “0” subsequently after setting it to “1” (reset).
3
0: User ROM area
1: Boot ROM area
Flash memory reset
bit (Note 2)
0: Normal operation
1: Reset
CPU rewrite mode
entry flag
0: Normal mode
1: CPU rewrite mode
0 : Normal mode (Software
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
1