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参数资料
| 型号： | M38869FFAHP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 5 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 60/113页 |
| 文件大小： | 1871K |
| 代理商： | M38869FFAHP |
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47
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[I2C START/STOP Condition Control Register
(S2D)] 001716
The I2C START/STOP condition control register (address 001716)
controls START/STOP condition detection.
Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 13.
Do not set “000002” or an odd number to the START/STOP condi-
tion set bit (SSC4 to SSC0).
Refer to Table 14, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or SDA
pin interrupt pin.
Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note: When changing the setting of the SCL/SDA interrupt pin polarity se-
lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS
interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the inter-
rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/
SDA interrupt pin selection bit, or the I2C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
Bit 7: START/STOP condition generating selection bit
(STSPSEL)
Setup/Hold time when the START/STOP condition is generated
can be selected.
Cycle number of system clock becomes standard for setup/hold
time. Additionally, setup/hold time is different between the START
condition and the STP condition. (Refer to Tables 11 and 12.) Set
“1” to this bit when the system clock frequency is 4 MHz or more.
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I2C control register (address 001516) to “0.” The first 7-bit
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I2C address register
(address 001316). At the time of this comparison, address com-
parison of the RBW bit of the I2C address register (address
001316) is not performed. For the data transmission format
when the 7-bit addressing format is selected, refer to Figure 46,
(1) and (2).
10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I2C control register (address 001516) to “1.” An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I2C address register (address 001316). At the time of this
comparison, an address comparison between the RBW bit of
the I2C address register (address 001316) and the R/W bit
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RBW bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is pro-
cessed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I2C status register (address 001416) is set to
“1.” After the second-byte address data is stored into the I2C
data shift register (address 001216), perform an address com-
parison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RBW bit of the I2C address register
(address 001316) to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are re-
ceived after a RESTART condition is detected, with the value of
the I2C address register (address 001316). For the data trans-
mission format when the 10-bit addressing format is selected,
refer to Figure 46, (3) and (4).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M38869FFAHP#UU | 功能描述:IC 740/3886 MCU FLASH 80LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 产品培训模块:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 标准包装:1 系列:M16C™ M32C/80/87 核心处理器:M32C/80 芯体尺寸:16/32-位 速度:32MHz 连通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外围设备:DMA，POR，PWM，WDT 输入/输出数:121 程序存储器容量:384KB（384K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:24K x 8 电压 - 电源 (Vcc/Vdd):3 V ~ 5.5 V 数据转换器:A/D 34x10b，D/A 2x8b 振荡器型:内部 工作温度:-20°C ~ 85°C 封装/外壳:144-LQFP 包装:托盘 产品目录页面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
| M38869FF-XXXHP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869M1-XXXHP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869M2-XXXHP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869M3-XXXHP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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