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参数资料
型号： M38C29MC-XXXHP
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64
封装： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件页数： 13/91页
文件大小： 1867K
代理商： M38C29MC-XXXHP
19
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
INTERRUPTS
Interrupts occur by nineteen sources: six external, twelve internal,
and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by software. Interrupt re-
quest bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
s Notes on Interrupts
When the active edge of an external interrupt (INT0 – INT2, CNTR0
or CNTR1) is set or an interrupt source where several interrupt source
is assigned to the same vector address is switched, the correspond-
ing interrupt request bit may also be set. Therefore, take following
sequence:
(1) Disable the interrupt.
(2) Set the interrupt edge selection register (Timer X control reg-
ister for CNTR0, Timer Y mode register for CNTR1).
(3) Clear the set interrupt request bit to “0.”
(4) Enable the interrupt.
Interrupt Source
Reset (Note 2)
INT0
INT1
INT2
Key input
(key-on wakeup)
Serial I/O1 receive
Serial I/O1 transmit
Serial I/O2 receive
Serial I/O2 transmit
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
CNTR0
Timer Y
CNTR1
A-D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vector Addresses (Note 1)
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling
edge of INT0 input
At detection of either rising or falling
edge of INT1 input
At detection of either rising or falling
edge of INT2 input
At falling of ports P00–P03, P54–P57
input logical level AND
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit
shift or transmit buffer is empty
At completion of serial I/O2 data receive
At completion of serial I/O2 transmit
shift or transmit buffer is empty
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At detection of either rising or falling
edge of CNTR0 input
At timer Y underflow
At detection of either rising or falling
edge of CNTR1 input
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt (active edge selectable)
Valid when INT2 interrupt is selected
External interrupt (active edge selectable)
Valid when key input interrupt is selected
External interrupt (falling valid)
Valid only when serial I/O1 is selected
Valid only when serial I/O2 is selected
Valid only when timer 1 interrupt is selected
Valid only when timer 2 interrupt is selected
External interrupt (active edge selectable)
Valid when A-D conversion interrupt is se-
lected
Non-maskable software interrupt
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 7 Interrupt vector addresses and priority
Remarks
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