参数资料
型号: M38C80E1-XXXFP
厂商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 单芯片8位CMOS微机
文件页数: 21/51页
文件大小: 874K
代理商: M38C80E1-XXXFP
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write by setting the timer X mode
register.
(1) Timer Mode
When the timer X count source selection bit is
0
, the timer counts
f(X
IN
)/16 (or f(X
CIN
)/16 in low-speed mode). When it is
1
, the timer
counts f(X
IN
).
(2) Buzzer Output Mode
Each time the timer underflows, a signal output from the BEEP
+
pin
is inverted. When the BEEP- valid bit is
1
, the opposite phase of
BEEP+ signal is output from the BEEP- pin. When using the BEEP+
pin and the BEEP- pin, set ports shared with these pins to output.
(3) Event Counter Mode
The timer counts signals input through the CNTR
0
pin.
Except for this, the operation in event counter mode is the same as
in timer mode. When using a timer in this mode, set the port shared
with the CNTR
0
pin to input.
(4) Pulse Width Measurement Mode
When the timer X count source selection bit is
0
, the count source
is f(X
IN
)/16 (or f(X
CIN
)/16 in low-speed mode). When it is
1
, the
count source is f(X
IN
).
If CNTR
0
active edge switch bit is
0
, the timer counts while the
input signal of CNTR
0
pin is at
H
. If it is
1
, the timer counts while
the input signal of CNTR
0
pin is at
L
. When using a timer in this
mode, set the port shared with the CNTR
0
pin to input.
G
Timer X write control
If the timer X write control bit is
0
, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is
1
, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
I
Notes on CNTR
0
interrupt active edge selection
CNTR
0
interrupt active edge depends on the CNTR
0
active edge
switch bit.
Fig. 17 Structure of timer X mode register
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