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参数资料
| 型号： | M38C80E1-XXXFP |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 单芯片8位CMOS微机 |
| 文件页数： | 24/51页 |
| 文件大小： | 874K |
| 代理商： | M38C80E1-XXXFP |
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24
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchronous
(UART) serial I/O. A dedicated timer (baud rate generator) is also
provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O can be selected by setting the mode
selection bit of the serial I/O control register to
“
1
”
.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is started
by a write signal to the transmit/receive buffer registers.
Fig. 20 Block diagram of clock synchronous serial I/O
Fig. 21 Operation of clock synchronous serial I/O function
P
4
6
/
S
C
L
K
P
4
7
/
S
R
D
Y
P4
4
/R
X
D
P4
5
/T
X
D
f(
-
s
X
I
p
N
)
e
e
1/4
1/4
F/F
Serial I/O status register
S
e
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
8
1
6
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
h
i
s
t
e
r
R
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
R
I
)
Clock control circuit
S
i
f
t
c
l
o
c
k
Serial I/O
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C
16
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Clock control circuit
Falling-edge detector
Data bus
Address 0018
16
S
h
i
f
t
c
l
o
c
k
Transmit shift register shift completion flag (TSC)
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Transmit buffer empty flag (TBE)
Address 0019
16
Transmit interrupt request (TI)
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
Data bus
A
d
d
r
e
s
s
0
0
1
A
1
6
Transmit buffer register
Transmit shift register
(f
(
X
C
I
N
)
i
n
l
o
w
d
m
o
d
e
)
R
e
c
e
i
v
e
e
n
a
b
l
e
s
i
g
n
a
l
S
R
D
Y
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
e
r
r
u
n
t
e
c
t
i
o
T
B
E
=
0
T
T
B
S
E
C
=
=
1
0
Transmit/receive shift clock
(1/2 to 1/2048 of internal clock,
or an external clock)
S
r
e
i
a
l
o
u
t
p
u
t
T
X
D
S
e
r
i
a
l
i
n
p
u
t
R
X
D
W
b
r
i
f
t
e
e
r
s
r
i
e
g
n
g
a
i
s
l
t
e
t
o
r
r
(
e
a
c
d
e
d
i
r
v
e
e
s
/
s
t
r
a
0
n
0
s
1
m
8
1
i
6
)
t
u
f
O
d
v
e
n
e
r
r
o
r
(
O
E
)
Notes 1:
The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial
I/O control register.
2:
If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the T
X
D pin.
3:
The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes
“
1
”
.
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
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