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参数资料
| 型号： | M38C80EE-XXXFP |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 单芯片8位CMOS微机 |
| 文件页数： | 22/51页 |
| 文件大小： | 874K |
| 代理商： | M38C80EE-XXXFP |
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22
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer Mode
The timer counts f(X
IN
)/16 (or f(X
CIN
)/16 in low-speed mode).
(2) Period Measurement Mode
CNTR
1
interrupt request is generated at rising/falling edge of CNTR
1
pin input signal. Simultaneously, the value in timer Y latch is reloaded
in timer Y and timer Y continues counting down. Except for the above-
mentioned, the operation in period measurement mode is the same
as in timer mode.
The timer value just before the reloading at rising/falling of CNTR
1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR
1
pin input signal is found by CNTR
1
interrupt. When using a timer in this mode, set the port shared with
the CNTR
1
pin to input.
(3) Event Counter Mode
The timer counts signals input through the CNTR
1
pin.
Except for this, the operation in event counter mode is the same as
in timer mode. When using a timer in this mode, set the port shared
with the CNTR
1
pin to input.
(4) Pulse Width HL Continuously Measurement
Mode
CNTR
1
interrupt request is generated at both rising and falling edges
of CNTR
1
pin input signal. Except for this, the operation in pulse
width HL continuously measurement mode is the same as in period
measurement mode. When using a timer in this mode, set the port
shared with the CNTR
1
pin to input.
I
Notes on CNTR
1
interrupt active edge selection
CNTR
1
interrupt active edge depends on the CNTR
1
active edge
switch bit. However, in the pulse width HL continuously measure-
ment mode, CNTR
1
interrupt request is generated at both rising and
falling edges of CNTR
1
pin input signal regardless of the setting of
CNTR
1
active edge switch bit.
Fig. 18 Structure of timer Y mode register
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Internal clock
φ
in low-speed mode is X
CIN
divided by 2.
When the timer X operating mode bits are
“
00
”
or
“
11
”
, the timer X count source is
f(X
CIN
)/16. When the timer X operating mode bits are
“
01
”
, the timer X count source
is f(X
CIN
).
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