参数资料
型号: M38D5XGXFP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件页数: 8/142页
文件大小: 2004K
代理商: M38D5XGXFP
Rev.3.04
May 20, 2008
Page 105 of 134
REJ03B0158-0304
38D5 Group
Timing Requirements And Switching Characteristics
NOTES:
1. 80 ns in the frequency/2 mode.
2. 32 ns in the frequency/2 mode.
3. When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Table 30
Timing requirements (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta =
20 to 85°C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
tW(RESET)
Reset input “L” pulse width
2
s
tC(XIN)
Main clock input cycle time
4.5V
VCC 5.5V (1)
62.5
ns
4.0V
VCC < 4.5V
125
ns
tWH(XIN)
Main clock input “H” pulse
width
4.5V
VCC 5.5V (2)
25
ns
4.0V
VCC < 4.5V
50
ns
tWL(XIN)
Main clock input “L” pulse
width
4.5V
VCC 5.5V (2)
25
ns
4.0V
VCC < 4.5V
50
ns
tC(CNTR)
CNTR0, CNTR1 input cycle time
250
ns
tWH(CNTR)
CNTR0, CNTR1 input “H” pulse width
105
ns
tWL(CNTR)
CNTR0, CNTR1 input “L” pulse width
105
ns
tWH(INT)
INT00, INT01, INT10, INT11, INT2 input “H” pulse width
80
ns
tWL(INT)
INT00, INT01, INT10, INT11, INT2 input “L” pulse width
80
ns
tC(SCLK1)
Serial I/O1 clock input cycle time (3)
800
ns
tWH(SCLK1)
Serial I/O1 clock input “H” pulse width (3)
370
ns
tWL(SCLK1)
Serial I/O1 clock input “L” pulse width (3)
370
ns
tsu(RXD-SCLK1) Serial I/O1 input setup time
220
ns
th(SCLK1-RXD)
Serial I/O1 input hold time
100
ns
tC(SCLK2)
Serial I/O2 clock input cycle time
1000
ns
tWH(SCLK2)
Serial I/O2 clock input “H” pulse width
400
ns
tWL(SCLK2)
Serial I/O2 clock input “L” pulse width
400
ns
tsu(SIN2-SCLK2)
Serial I/O2 input setup time
200
ns
th(SCLK2-SIN2)
Serial I/O2 input hold time
200
ns
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