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| 型号： | M38K09F8LHP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 42/133页 |
| 文件大小： | 1359K |
| 代理商： | M38K09F8LHP |
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38K0 Group
Rev.3.00
Oct 05, 2006
page 16 of 129
REJ03B0192-0300
Interrupt Request
Generating Conditions
At reset
At detection of USB bus reset signal (2.5
s interval SE0)
At detection of USB SOF signal
At detection of resume signal (K state or SE0) or suspend signal (3
ms interval bus idle), or at completion of transaction
At completion of reception or transmission or at completion of DMA
transmission
At detection of either rising or falling edge of INT0 input
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or falling edge of INT1 input
(Note 4)
At completion of serial I/O data reception
At completion of serial I/O data transmission
At detection of either rising or falling edge of CNTR0 input
At falling of conjunction of input level for port P0 (at input mode)
At completion of A/D conversion
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Nothing is arranged in these vector addresses.
4: Fix bit 1 of interrupt control register 2 (address 003F16) to “0”.
INTERRUPTS
Interrupts occur by fifteen sources: four external, ten internal, and
one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source
Reset (Note 2)
USB bus reset
USB SOF
USB device
External bus
INT0
Timer X
Timer 1
Timer 2
INT1
(Note 3)
Serial I/O
reception
Serial I/O
transmission
CNTR0
Key-on wake up
A/D conversion
BRK instruction
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Table 6 Interrupt vector addresses and priority
Priority
1
2
3
4
5
6
7
8
9
10
—
11
12
13
14
15
16
Vector Addresses (Note 1)
sNotes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
When switching external interrupt active edge
Related register: Interrupt edge selection register (address
0FF316), Timer X mode register (address
002316)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit (active edge switch bit).
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
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