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参数资料
型号： M41ST84W-85MH6TR
厂商： STMICROELECTRONICS
元件分类： 时钟/数据恢复及定时提取
英文描述： 1 TIMER(S), REAL TIME CLOCK, PDSO28
封装： 0.330 INCH, SNAPHAT, PLASTIC, SOH-28
文件页数： 3/32页
文件大小： 168K
代理商： M41ST84W-85MH6TR
11/32
M41ST84Y, M41ST84W
Read Mode
In this mode the master reads the M41ST84Y/W
slave after setting the slave address (see Figure
10, page 12). Following the write mode control bit
(R/W=0) and the acknowledge bit, the word ad-
dress ‘An’ is written to the on-chip address pointer.
Next the START condition and slave address are
repeated followed by the READ mode control bit
(R/W=1). At this point the master transmitter be-
comes the master receiver. The data byte which
was addressed will be transmitted and the master
receiver will send an acknowledge bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an acknowledge bit. The
M41ST84Y/W slave transmitter will now place the
data byte at address An+1 on the bus, the master
receiver reads and acknowledges the new byte
and the address pointer is incremented to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure 11,
page 12).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a RAM address.
An alternate READ mode may also be implement-
ed whereby the master reads the M41ST84Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure 12, page 12).
Write Mode
In this mode the master transmitter transmits to
the M41ST84Y/W slave receiver. Bus protocol is
shown in Figure Figure 13, page 13. Following the
START condition and slave address, a logic ‘0’ (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST84Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
10, page 12) and again after it has received the
word address and each data byte.
Data Retention Mode
With valid VCC applied, the M41ST84Y/W can be
accessed as described above with read or write
cycles. Should the supply voltage decay, the
M41ST84Y/W will automatically deselect, write
protecting itself when VCC falls between VPFD
(max) and VPFD (min). This is accomplished by in-
ternally inhibiting access to the clock registers. At
this time, the Reset pin (RST) is driven active and
will remain active until VCC returns to nominal lev-
els. When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the SNAPHAT (or external)
battery and the clock registers and SRAM are
maintained from the attached battery supply.
All outputs become high impedance. On power up,
when VCC returns to a nominal value, write protec-
tion continues for tREC. The RST signal also re-
mains active during this time (see Figure 21, page
25).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Battery Low Warning
The M41ST84Y/W automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT top
may be replaced while VCC is applied to the de-
vice.
Note: This will cause the clock to lose time during
the interval the SNAPHAT battery/crystal top is
disconnected.
The M41ST84Y/W only monitors the battery when
a nominal VCC is applied to the device. Thus appli-
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
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