参数资料
型号: M41ST85Y-70MH6
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO28
封装: 0.330 INCH, SNAPHAT, PLASTIC, SOH-28
文件页数: 13/32页
文件大小: 171K
代理商: M41ST85Y-70MH6
M41ST85Y, M41ST85W
20/32
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an in-
ternal reference voltage (independent from the
VPFD comparator). If PFI is less than the power-fail
threshold (VPFI), the Power-Fail Output (PFO) will
go low. This function is intended for use as an un-
dervoltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see Figure 4, page 6) to either the
unregulated DC input (if it is available) or the reg-
ulated output of the VCC regulator. The voltage di-
vider can be set up such that the voltage at PFI
falls below VPFI several milliseconds before the
regulated VCC input to the M41ST85Y/W or the mi-
croprocessor drops below the minimum operating
voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This oc-
curs after VCC drops below VPFD(min). When pow-
er returns, PFO is forced high, irrespective of VPFI
for the write protect time (tREC), which is the time
from VPFD(max) until the inputs are recognized. At
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to VSS and PFO
left unconnected.
Calibrating the Clock
The M41ST85Y/W is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not exceed +/–35 PPM
(parts per million) oscillator frequency error at
25oC, which equates to about +/–1.53 minutes per
month. When the Calibration circuit is properly em-
ployed, accuracy improves to better than +1/–2
PPM at 25
°C.
The oscillation rate of crystals changes with tem-
perature (see Figure 17, page 21). Therefore, the
M41ST85Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure 18, page 21.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register (8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; ‘1’ indi-
cates positive calibration, ‘0’ indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary ‘1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41ST85Y/W may re-
quire.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that ac-
cesses the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT/OUT pin. The pin will toggle at 512Hz,
when the Stop bit (ST, D7 of 1h) is ‘0’,the Frequen-
cy Test bit (FT, D6 of 8h) is ‘1’, the Alarm Flag En-
able bit (AFE, D7 of Ah) is ‘0’, and the Watchdog
Steering bit (WDS, D7 of 9h) is ‘1’ or the Watchdog
Register (9h=0) is reset.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature.
For
example,
a
reading
of
512.010124 Hz would indicate a +20 PPM oscilla-
tor frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequen-
cy.
The IRQ/FT/OUT pin is an open drain output
which requires a pull-up resistor to VCC for proper
operation. A 500 to10k resistor is recommended in
order to control the rise time. The FT bit is cleared
on power-down.
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