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参数资料
| 型号： | M41ST85Y-70MH6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封装： | 0.330 INCH, SNAPHAT, PLASTIC, SOH-28 |
| 文件页数： | 3/32页 |
| 文件大小： | 171K |
| 代理商： | M41ST85Y-70MH6 |
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M41ST85Y, M41ST85W
Read Mode
In this mode the master reads the M41ST85Y/W
slave after setting the slave address (see Figure
10, page 12). Following the write mode control bit
(R/W=0) and the acknowledge bit, the word ad-
dress ‘An’ is written to the on-chip address pointer.
Next the START condition and slave address are
repeated followed by the READ mode control bit
(R/W=1). At this point the master transmitter be-
comes the master receiver.
The data byte which was addressed will be trans-
mitted and the master receiver will send an ac-
knowledge bit to the slave transmitter. The
address pointer is only incremented on reception
of an acknowledge bit. The M41ST85Y/W slave
transmitter will now place the data byte at address
An+1 on the bus, the master receiver reads and
acknowledges the new byte and the address
pointer is incremented to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure 11,
page 12).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a RAM address.
An alternate READ mode may also be implement-
ed whereby the master reads the M41ST85Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure 12, page 12).
Write Mode
In this mode the master transmitter transmits to
the M41ST85Y/W slave receiver. Bus protocol is
shown in Figure 13, page 13. Following the
START condition and slave address, a logic ‘0’ (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST85Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
10, page 12) and again after it has received the
word address and each data byte.
Battery Low Warning
The M41ST85Y/W automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up
sequence, this indicates that the battery is below
approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT top
may be replaced while VCC is applied to the
device.
Note: This will cause the clock to lose time during
the interval the SNAPHAT battery/crystal top is
disconnected.
The M41ST85Y/W only monitors the battery when
a nominal VCC is applied to the device. Thus appli-
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M41ST85YMH | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR |
| M41ST85YMH6 | 功能描述:实时时钟 Serial 512 (64x8) RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| M41ST85YMH6E | 功能描述:IC RTC 5.0V 512BIT NVRAM 28SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 实时时钟 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 类型:时钟/日历 特点:警报器，闰年，SRAM 存储容量:- 时间格式:HH:MM:SS（12/24 小时） 数据格式:YY-MM-DD-dd 接口:SPI 电源电压:2 V ~ 5.5 V 电压 - 电源，电池:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN EP 包装:管件 |
| M41ST85YMH6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR |
| M41ST85YMX | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR |
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