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参数资料
| 型号： | M41T11MH6TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封装： | 0.330 INCH, SNAPHAT, PLASTIC, SOH-28 |
| 文件页数： | 3/24页 |
| 文件大小： | 355K |
| 代理商： | M41T11MH6TR |
11/24
M41T11
CLOCK OPERATION
The eight byte clock register (see Table 3) is used
to both set the clock and to read the date and time
from the clock, in a binary coded decimal format.
Seconds, Minutes, and Hours are contained within
the first three registers. Bits D6 and D7 of clock
register 2 (Hours Register) contain the CENTURY
ENABLE Bit (CEB) and the CENTURY Bit (CB).
Setting CEB to a '1' will cause CB to toggle, either
from '0' to '1' or from '1' to '0' at the turn of the cen-
tury (depending upon its initial state). If CEB is set
to a '0', CB will not toggle. Bits D0 through D2 of
register 3 contain the Day (day of week). Registers
4, 5 and 6 contain the Date (day of month), Month
and Years. The final register is the Control Regis-
ter (this is described in the Clock Calibration sec-
tion). Bit D7 of register 0 contains the STOP Bit
(ST). Setting this bit to a '1' will cause the oscillator
to stop. If the device is expected to spend a signif-
icant amount of time on the shelf, the oscillator
may be stopped to reduce current drain. When re-
set to a '0' the oscillator restarts within one second.
Note: In order to guarantee oscillator start-up after
the initial power-up, set the ST Bit to a '1,' then re-
set this bit to a '0.' This sequence enables a “kick
start” circuit which aids the oscillator start-up dur-
ing worst case conditions of voltage and tempera-
ture.
The seven Clock Registers may be read one byte
at a time, or in a sequential block. The Control
Register (Address location 7) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
seven clock addresses are being read. If a clock
address is being read, an update of the clock reg-
isters will be delayed by 250ms to allow the read
to be completed before the update occurs. This
will prevent a transition of data during the read.
Note: This 250ms delay affects only the clock reg-
ister update and does not alter the actual clock
time.
Table 3. Register Map
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
ST = STOP Bit
OUT = Output level
X = Don’t care
CEB = Century Enable Bit
CB = Century Bit
Note: 1. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the initial value set).
When CEB is set to '0', CB will not toggle.
Address
Data
Function/Range
BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
0
ST
10 Seconds
Seconds
00-59
1
X
10 Minutes
Minutes
00-59
2
CEB (1)
CB
10 Hours
Hours
Century/Hours
0-1/00-23
3
XXX
XX
Day
01-07
4
X
10 Date
Date
01-31
5
X
10 M.
Month
01-12
6
10 Years
Years
Year
00-99
7
OUT
FT
S
Calibration
Control
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