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参数资料
| 型号： | M470L6423EN0-A2 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512MB Unbuffered SODIMM(based on sTSOP) |
| 中文描述： | 512MB的无缓冲的SODIMM（基于sTSOP） |
| 文件页数： | 10/13页 |
| 文件大小： | 145K |
| 代理商： | M470L6423EN0-A2 |
DDR SDRAM
512MB Unbuffered SODIMM(based on sTSOP)
Rev. 1.3 March. 2004
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with t
RCD
satisfied after this command.
5. For registered DIMMs, t
CL
and t
CH
are
≥
45% of the period including both the half period jitter (t
JIT(HP)
) of the PLL and the half period
jitter due to crosstalk (t
JIT
(crosstalk)
) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
tIS
tIH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
This derating table is used to increase t
IS
/t
IH
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
(V/ns)
0.5
0.4
0.3
This derating table is used to increase t
DS
/t
DH
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Parameter
Symbol
B3
A2
B0
Unit
Note
Min
Max
Min
Max
Min
Max
Mode register set cycle time
tMRD
12
15
15
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
ns
7,8,9
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
ns
7,8,9
Control & Address input pulse width
tIPW
2.2
2.2
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
1.75
1.75
ns
Power down exit time
tPDEX
6
7.5
7.5
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
ns
4
Exit self refresh to read command
tXSRD
200
200
200
tCK
Refresh interval time
tREFI
7.8
7.8
7.8
us
1
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
5
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
Data hold skew factor
tQHS
0.55
0.75
0.75
ns
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
3
Active to Read with Auto precharge
command
tRAP
18
20
20
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
11
tDS
(ps)
0
+75
+150
tDH
(ps)
0
+75
+150
相关PDF资料 |
PDF描述 |
|---|---|
| M470L6423EN0-B0 | 512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CB3 | 512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CLB3 | 512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6524CU0 | DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb C-die |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M470L6423EN0-B0 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CB3 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CLB3 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6524BT0-CA2 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
| M470L6524BT0-CB0 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
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