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参数资料
| 型号： | M470L6423EN0-A2 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512MB Unbuffered SODIMM(based on sTSOP) |
| 中文描述： | 512MB的无缓冲的SODIMM（基于sTSOP） |
| 文件页数： | 9/13页 |
| 文件大小： | 145K |
| 代理商： | M470L6423EN0-A2 |
DDR SDRAM
512MB Unbuffered SODIMM(based on sTSOP)
Rev. 1.3 March. 2004
AC Timming Parameters & Specifications
Parameter
Symbol
B3
(DDR333@CL=2.5))
A2
(DDR266@CL=2.0)
B0
(DDR266@CL=2.5))
Unit
Note
Mn
Max
Mn
Max
Mn
Max
Row cycle time
tRC
60
65
65
ns
Refresh row cycle time
tRFC
72
75
75
ns
Row active time
tRAS
42
70K
45
120K
45
120K
ns
RAS to CAS delay
tRCD
18
20
20
ns
Row precharge time
tRP
18
20
20
ns
Row active to Row active delay
tRRD
12
15
15
ns
Write recovery time
tWR
15
15
15
ns
Last data in to Read command
tWTR
1
1
1
tCK
Col. address to Col. address delay
tCCD
1
1
1
tCK
Clock cycle time
CL=2.0
tCK
7.5
12
7.5
12
10
12
ns
CL=2.5
6
12
7.5
12
7.5
12
ns
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time fromCK/CK
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time fromCK/CK
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.45
-
0.5
-
0.5
ns
12
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
3
DQS-in hold time
tWPRE
0.25
0.25
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge fromCK rising-hold time
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input setup time(fast)
tIS
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input hold time(fast)
tIH
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input setup time(slow)
tIS
0.8
1.0
1.0
ns
i, 6~9
Address and Control Input hold time(slow)
tIH
0.8
1.0
1.0
ns
i, 6~9
Data-out high impedence time fromCK/CK
tHZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
1
Data-out low impedence time fromCK/CK
tLZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
1
Input Slew Rate(for input only pins)
tSL(I)
0.5
0.5
0.5
V/ns
Input Slew Rate(for I/O pins)
tSL(IO)
0.5
0.5
0.5
V/ns
Output Slew Rate(x4,x8)
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
V/ns
Output Slew Rate Matching Ratio(rise to fall)
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
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| M470L6423EN0-B0 | 512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CB3 | 512MB Unbuffered SODIMM(based on sTSOP) |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M470L6423EN0-B0 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CB3 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6423EN0-CLB3 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512MB Unbuffered SODIMM(based on sTSOP) |
| M470L6524BT0-CA2 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
| M470L6524BT0-CB0 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
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