参数资料
型号: M470T6554CZ0-E6
厂商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR2 Unbuffered SODIMM
中文描述: 无缓冲DDR2内存的SODIMM
文件页数: 14/20页
文件大小: 270K
代理商: M470T6554CZ0-E6
Rev. 1.1 Mar. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
DDR2 SDRAM
Parameter
Symbol
DDR2-667
DDR2-533
DDR2-400
Units
min
max
min
max
min
max
DQ and DM input
setup time
tDS(base)
100
x
100
x
150
x
ps
Control & Address
input pulse width for
each input
tIPW
0.6
x
0.6
x
0.6
x
tCK
DQ and DM input
pulse width for each
input
tDIPW
0.35
x
0.35
x
0.35
x
tCK
Data-out high-
impedance time from
CK/CK
tHZ
x
tAC
max
x
tAC
max
x
tAC
max
ps
DQS low-impedance
time from CK/CK
tLZ(DQS)
tAC
min
tAC
max
tAC
min
tAC
max
tAC
min
tAC
max
ps
DQ low-impedance
time from CK/CK
tLZ(DQ)
2*tAC
min
tAC
max
2* tAC
min
tAC
max
2* tAC
min
tAC
max
ps
DQS-DQ skew for
DQS and associated
DQ signals
tDQSQ
x
240
x
300
x
350
ps
DQ hold skew factor
tQHS
x
340
x
400
x
450
ps
DQ/DQS output hold
time from DQS
tQH
tHP -
tQHS
x
tHP -
tQHS
x
tHP -
tQHS
x
ps
Write command to first
DQS latching transition
tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
DQS input high pulse
width
tDQSH
0.35
x
0.35
x
0.35
x
tCK
DQS input low pulse
width
tDQSL
0.35
x
0.35
x
0.35
x
tCK
DQS falling edge to
CK setup time
tDSS
0.2
x
0.2
x
0.2
x
tCK
DQS falling edge hold
time from CK
tDSH
0.2
x
0.2
x
0.2
x
tCK
Mode register set
command cycle time
tMRD
2
x
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
x
0.35
x
0.35
x
tCK
Address and control
input hold time
tIH(base)
275
x
375
x
475
x
ps
Address and control
input setup time
tIS(base)
200
x
250
x
350
x
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Active to active
command period for
1KB page size
products
tRRD
7.5
x
7.5
x
7.5
x
ns
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