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参数资料
| 型号： | M48T02-70PC1 |
| 厂商： | 意法半导体 |
| 英文描述： | 16 Kbit 2Kb x8 TIMEKEEPER[ SRAM |
| 中文描述： | 16千位2KB的x8计时器[静态存储器 |
| 文件页数： | 7/15页 |
| 文件大小： | 94K |
| 代理商： | M48T02-70PC1 |
Symbol
Parameter
M48T02 / M48T12
Unit
-70
-150
-200
Min
Max
Min
Max
Min
Max
t
AVAV
Write Cycle Time
70
150
200
ns
t
AVWL
Address Valid to Write Enable Low
0
0
0
ns
t
AVEL
Address Valid to Chip Enable Low
0
0
0
ns
t
WLWH
Write Enable Pulse Width
50
90
120
ns
t
ELEH
Chip Enable Low to Chip Enable High
55
90
120
ns
t
WHAX
Write Enable High to Address Transition
0
10
10
ns
t
EHAX
Chip Enable High to Address Transition
0
10
10
ns
t
DVWH
Input Valid to Write Enable High
30
40
60
ns
t
DVEH
Input Valid to Chip Enable High
30
40
60
ns
t
WHDX
Write Enable High to Input Transition
5
5
5
ns
t
EHDX
Chip Enable High to Input Transition
5
5
5
ns
t
WLQZ
Write Enable Low to Output Hi-Z
25
50
60
ns
t
AVWH
Address Valid to Write Enable High
60
120
140
ns
t
AVEH
Address Valid to Chip Enable High
60
120
140
ns
t
WHQX
Write Enable High to Output Transition
5
10
10
ns
Table10. Write Mode AC Characteristics
(T
A
= 0 to 70
°
C; V
CC
= 4.75V to 5.5Vor 4.5V to 5.5V)
READMODE
The M48T02/12 is in theRead Mode wheneverW
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
addressinput signal is stable,providing that the E
andG accesstimes are alsosatisfied. If the E and
G access times are not met, valid data will be
availableafterthe latterof theChipEnableAccess
time (t
ELQV
) or OutputEnable Accesstime(t
GLQV
).
The state of the eight three-stateData I/O signals
iscontrolledbyEandG. Iftheoutputsareactivated
before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time(t
AXQX
) but will go indeterminateuntil the next
AddressAccess.
WRITE MODE
The M48T02/12 is in the Write Mode wheneverW
and E are active. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
orE. The addressesmustbe held validthroughout
the cycle. E or W must return high for a minimum
of t
EHAX
from Chip Enable or t
WHAX
from Write
Enablepriortotheinitiationof anotherreador write
cycle. Data-inmustbe validt
DVWH
priorto the end
of write and remain valid for t
WHDX
afterward. G
shouldbe kepthighduringwritecyclesto avoidbus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disablethe outputs t
WLQZ
after W falls.
7/15
M48T02, M48T12
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T02-70PC1 | 制造商:STMicroelectronics 功能描述:IC NVRAM 10 YR BATTERY 16K 48T02 |
| M48T02-70PC1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0V, 16 Kbit (2Kb x 8) TIMEKEEPER㈢ SRAM |
| M48T08 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V, 64Kbit (8 Kb x 8) TIMEKEEPER㈢ SRAM |
| M48T08_07 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V, 64Kbit (8 Kb x 8) TIMEKEEPER㈢ SRAM |
| M48T08_10 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5 V, 64 Kbit (8 Kb x 8) TIMEKEEPER?? SRAM |
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