参数资料
型号: M48T129Y-85CS1
厂商: 意法半导体
元件分类: SRAM
英文描述: 3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM
中文描述: 3.3 - 5V的1兆位的SRAM 128KB的x8计时器
文件页数: 10/22页
文件大小: 140K
代理商: M48T129Y-85CS1
M48T129Y, M48T129V
10/22
Table 10. Write Mode AC Characteristics
(T
A
= 0 to 70
°
C)
Note: 1. C
= 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Symbol
Parameter
M48T129Y
M48T129V
Unit
-70
-85
Min
Max
Min
Max
t
AVAV
Write Cycle Time
70
85
ns
t
AVWL
Address Valid to Write Enable Low
0
0
ns
t
AVEL
Address Valid to Chip Enable Low
0
0
ns
t
WLWH
Write Enable Pulse Width
50
60
ns
t
ELEH
Chip Enable Low toChip Enable High
55
65
ns
t
WHAX
Write Enable High to Address Transition
5
5
ns
t
EHAX
Chip Enable High to Address Transition
10
15
ns
t
DVWH
Input Valid to Write Enable High
30
35
ns
t
DVEH
Input Valid to Chip Enable High
30
35
ns
t
WHDX
Write Enable High to Input Transition
5
5
ns
t
EHDX
Chip Enable High to Input Transition
10
15
ns
t
WLQZ(1, 2)
Write Enable Low to Output Hi-Z
25
30
ns
t
AVWH
Address Valid to Write Enable High
60
70
ns
t
AVEH
Address Valid to Chip Enable High
60
70
ns
t
WHQX(1, 2)
Write Enable High to Output Transition
5
5
ns
WATCHDOG TIMER
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
1FFF7h. Bits BMB4-BMB0 store abinary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 sec-
ond, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note:
Accuracy of timer is within
±
the selected
resolution.
If theprocessor does notreset the timer within the
specified period, the M48T129Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading theFlags Register (Address1FFF0h). The
most significantbit of the Watchdog Register is the
Watchdog Steering Bit (WDS). When set to a ’0’,
the watchdog will activate the IRQ/FT pin when
timed-out. WhenWDS is set to a ’1’, the watchdog
will output a negative pulse on the RST pin for 40
to 200 ms. The Watchdog register and the FT bit
will reset to a ’0’at the end of a Watchdog time-out
when the WDSbit is set to a ’1’. The watchdog tim-
er can be reset by having the original time-out pe-
riod
re-written
into
the
effectively restarting the count-down cycle.
Should the watchdog timer time-out,and theWDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
1FFF0h). The watchdog function is automatically
disabled upon power-down and the Watchdog
Register is cleared. If the watchdog function is set
to output to the IRQ/FT pin and the frequency test
function is activated, the watchdog or alarm func-
tion prevails and the frequency test function is de-
nied.
Watchdog Register,
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