参数资料
型号: M48T201V-85MH1F
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO44
封装: SNAPHAT, ROHS COMPLIANT, PLASTIC, SOIC-44
文件页数: 13/37页
文件大小: 311K
代理商: M48T201V-85MH1F
Clock operation
M48T201Y, M48T201V
Figure 8.
Backup mode alarm waveforms
3.6
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of timeout into the Watchdog
Register, address 7FFF7h. Bits BMB4-BMB0 store a binary multiplier and the two lower
order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1
second, and 11 = 4 seconds. The amount of timeout is then determined to be the
multiplication of the five-bit multiplier value with the resolution. (For example: writing
00001110 in the watchdog register = 3*1 or 3 seconds).
Note:
Accuracy of timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M48T201Y/V sets
the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.
WDF is reset by reading the flag register (address 7FFF0h).
The most significant bit of the watchdog register is the watchdog steering bit (WDS). When
set to a '0', the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a
'1,' the watchdog will output a negative pulse on the RST pin for tREC. The watchdog register
and the AFE, SQWE, ABE, and FT bits will reset to a '0' at the end of a watchdog timeout
when the WDS bit is set to a '1.'
The watchdog timer can be reset by two methods:
1.
a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI)
or
2.
the microprocessor can perform a WRITE of the watchdog register.
The timeout period then starts over. The WDI pin should be tied to VSS if not used. The
watchdog will be reset on each transition (edge) seen by the WDI pin.
AI03520
VCC
IRQ/FT
HIGH-Z
VPFD (max)
VPFD (min)
AFE bit/ABE bit
AF bit in Flags Register
HIGH-Z
VSO
tREC
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