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参数资料
| 型号： | M48T201V-85MH1F |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封装： | SNAPHAT, ROHS COMPLIANT, PLASTIC, SOIC-44 |
| 文件页数： | 7/37页 |
| 文件大小： | 311K |
| 代理商： | M48T201V-85MH1F |
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M48T201Y, M48T201V
Operation
Table 4.
Write mode AC characteristics
2.4
Data retention mode
With valid VCC applied, the M48T201Y/V can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the M48T201Y/V will automatically
deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD
(max) and VPFD (min). This is accomplished by internally inhibiting access to the clock
registers via the E signal. At this time, the reset pin (RST) is driven active and will remain
active until VCC returns to nominal levels. External RAM access is inhibited in a similar
manner by forcing ECON to a high level. This level is within 0.2 V of the VBAT. ECON will
remain at this level as long as VCC remains at an out-of-tolerance condition. When VCC falls
below the level of the battery (VBAT), power input is switched from the VCC pin to the
SNAPHAT battery and the clock registers are maintained from the attached battery supply.
External RAM is also powered by the SNAPHAT battery. All outputs except GCON, ECON,
RST, IRQ/FT and VOUT, become high impedance. The VOUT pin is capable of supplying
100 A of current to the attached memory with less than 0.3 V drop under this condition. On
power up, when VCC returns to a nominal value, write protection continues for 200 ms (max)
page 30).
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
M48T201Y
M48T201V
Unit
–70
–85
Min
Max
Min
Max
tAVAV
WRITE cycle time
70
85
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH
WRITE enable pulse width
45
55
ns
tELEH
Chip enable low to chip enable high
50
60
ns
tWHAX
WRITE enable high to address transition
0
ns
tEHAX
Chip enable high to address transition
0
ns
tDVWH
Input valid to WRITE enable high
25
30
ns
tDVEH
Input valid to chip enable high
25
30
ns
tWHDX
WRITE enable high to input transition
0
ns
tEHDX
Chip enable high to input transition
0
ns
tWLQZ
(2)(3)
2.
CL = 5 pF
3.
If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output High-Z
20
25
ns
tAVWH
Address valid to WRITE enable high
55
65
ns
tAVEH
Address valid to chip enable high
55
65
ns
tWHQX
WRITE enable high to output transition
5
ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T201V-85MH1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3V TIMEKEEPER㈢ supervisor |
| M48T201VMH | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V TIMEKEEPER CONTROLLER |
| M48T201VSH | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V TIMEKEEPER CONTROLLER |
| M48T201Y | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:3.3V-5V TIMEKEEPER CONTROLLER |
| M48T201Y_07 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.3V TIMEKEEPER㈢ supervisor |
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