参数资料
型号: M48T212V-70MH1TR
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封装: SNAPHAT, PLASTIC, SO-44
文件页数: 2/23页
文件大小: 150K
代理商: M48T212V-70MH1TR
M48T212Y, M48T212V
10/23
Figure 8. Write Cycle Timing: RTC Control Signals
AI02641
W
DQ0-DQ7
G
DATA IN
VALID
ADDRESS
tAVAV
E
tAVEH
tAVAV
WRITE
READ
DATA OUT
VALID
DATA OUT
VALID
tAVWH
tAVQV
tWLWH
tWHDX
tWHAX
tWHQX
tWLQZ
tDVWH
tGLQV
tEHQZ
tDVEH
DATA IN
VALID
tELEH
tEHAX
tAVEL
tEHDX
tAVWL
WRITE MODE
The M48T212Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are in a low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W or E. A write is terminated by the
earlier rising edge of W or E. The addresses must
be held valid throughout the cycle. E or W must re-
turn high for a minimum of tEHAX from Chip Enable
or tWHAX from Write Enable prior to the initiation of
another read or write cycle. Data-in must be valid
tDVWH prior to the end of write and remain valid for
tWHDX afterward.
G should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs tWLQZ after W falls.
When E is low during the write, one of the on-
board TIMEKEEPER registers will be selected and
data will be written into the device. When EX is low
(and E is high) an external SRAM location is se-
lected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
相关PDF资料
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