参数资料
型号: M48T212V-70MH6TR
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封装: SNAPHAT, PLASTIC, SO-44
文件页数: 3/23页
文件大小: 150K
代理商: M48T212V-70MH6TR
11/23
M48T212Y, M48T212V
Table 11. Write Mode AC Characteristics
(TA = 0 to 70°C)
Note: 1. CL = 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Symbol
Parameter
M48T212Y
M48T212V
Unit
-70
-85
Min
Max
Min
Max
tAVAV
Write Cycle Time
70
85
ns
tAVWL
Address Valid to Write Enable Low
0
ns
tAVEL
Address Valid to Chip Enable Low
0
ns
tWLWH
Write Enable Pulse Width
45
55
ns
tELEH
Chip Enable Low to Chip Enable High
50
60
ns
tWHAX
Write Enable High to Address Transition
0
ns
tEHAX
Chip Enable High to Address Transition
0
ns
tDVWH
Input Valid to Write Enable High
25
30
ns
tDVEH
Input Valid to Chip Enable High
25
30
ns
tWHDX
Write Enable High to Input Transition
0
ns
tEHDX
Chip Enable High to Input Transition
0
ns
tWLQZ
(1,2)
Write Enable Low to Output High-Z
20
25
ns
tAVWH
Address Valid to Write Enable High
55
65
ns
tAVEH
Address Valid to Chip Enable High
55
65
ns
tWHQX
(1,2)
Write Enable High to Output Transition
5
ns
DATA RETENTION MODE
With valid VCC applied, the M48T212Y/V can be
accessed as described above with read or write
cycles. Should the supply voltage decay, the
M48T212Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCC falls between VPFD (max) and VPFD (min).
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E1CON and E2CON to a high level.
This level is within 0.2 volts of the VBAT.E1CON
and E2CON will remain at this level as long as VCC
remains at an out-of tolerance condition.
When VCC falls below the level of the battery
(VBAT), power input is switched from the VCC pin
to the SNAPHAT battery and the clock registers
and external SRAM are maintained from the at-
tached battery supply. All outputs become high im-
pedance. The VOUT pin is capable of supplying
100
A of current to the attached memory with less
than 0.3V drop under this condition. On power up,
when VCC returns to a nominal value, write protec-
tion continues for 200ms (max) by inhibiting
E1CON or E2CON.
The RST signal also remains active during this
time (see Figure 5).
Note: Most low power SRAMs on the market to-
day can be used with the M48T212Y/V TIME-
KEEPER Controller. There are, however some
criteria which should be used in making the final
choice of an SRAM to use. The SRAM must be de-
signed in a way where the chip enable input dis-
ables all other inputs to the SRAM. This allows
inputs to the M48T212Y/V and SRAMs to be Don’t
Care once VCC falls below VPFD(min). The SRAM
should also guarantee data retention down to
VCC = 2.0V. The chip enable access time must be
sufficient to meet the system needs with the chip
enable output propagation delays included.
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