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参数资料
| 型号： | M48T212Y-70MH1TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封装： | 0.330 INCH, PLASTIC, SOH-44 |
| 文件页数： | 5/32页 |
| 文件大小： | 473K |
| 代理商： | M48T212Y-70MH1TR |
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M48T212Y, M48T212V
Data Retention Mode
With valid VCC applied, the M48T212Y/V can be
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M48T212Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCC falls between VPFD (max) and VPFD (min).
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E1CON and E2CON to a high level.
This level is within 0.2 volts of the VBAT. E1CON
and E2CON will remain at this level as long as VCC
remains at an out-of-tolerance condition.
When VCC falls below battery back-up switchover
voltage (VSO), power input is switched from the
VCC pin to the SNAPHAT
battery and the clock
registers and external SRAM are maintained from
the attached battery supply. All outputs become
high impedance. The VOUT pin is capable of sup-
plying 100A of current to the attached memory
with less than 0.3V drop under this condition. On
power up, when VCC returns to a nominal value,
write protection continues for 200ms (max) by in-
hibiting E1CON or E2CON.
The RST signal also remains active during this
time (see Figure 15., page 26).
Note: Most low power SRAMs on the market to-
day can be used with the M48T212Y/V TIME-
KEEPER SUPERVISOR. There are, however
some criteria which should be used in making the
final choice of an SRAM to use. The SRAM must
be designed in a way where the chip enable input
disables all other inputs to the SRAM. This allows
inputs to the M48T212Y/V and SRAMs to be
“Don't care” once VCC falls below VPFD(min). The
SRAM should also guarantee data retention down
to VCC = 2.0V. The chip enable access time must
be sufficient to meet the system needs with the
chip enable output propagation delays included.
If the SRAM includes a second chip enable pin
(E2), this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion
current
specifications
for
the
particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
The data retention current value of the SRAMs can
then be added to the IBAT value of the M48T212Y/
V to determine the total current requirements for
data retention. The available battery capacity for
the SNAPHAT of your choice can then be divided
by this current to determine the amount of data re-
tention available (see Table 20., page 30).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
相关PDF资料 |
PDF描述 |
|---|---|
| M48T212Y-70MH1F | REAL TIME CLOCK, PDSO44 |
| M48T212Y-70MH1 | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| M48T212V-85MH6E | REAL TIME CLOCK, PDSO44 |
| M48T212V-85MH6F | REAL TIME CLOCK, PDSO44 |
| M48T212Y-70MH6 | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M48T212Y-70MH6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V/3.3V TIMEKEEPER[ CONTROLLER |
| M48T212Y-70MH6E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V/3.3V TIMEKEEPER CONTROLLER Supervisor |
| M48T212Y-70MH6F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V/3.3V TIMEKEEPER CONTROLLER Supervisor |
| M48T212Y-70MH6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V/3.3V TIMEKEEPER[ CONTROLLER |
| M48T212Y-85MH1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5V/3.3V TIMEKEEPER[ CONTROLLER |
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