参数资料
型号: M48T212Y-70MH6TR
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封装: 0.330 INCH, PLASTIC, SOH-44
文件页数: 31/32页
文件大小: 473K
代理商: M48T212Y-70MH6TR
M48T212Y, M48T212V
8/32
OPERATION
Automatic backup and write protection for an ex-
ternal SRAM is provided through VOUT, E1CON
and E2CON pins. (Users are urged to insure that
voltage specifications, for both the SUPERVISOR
chip and external SRAM chosen, are similar). The
SNAPHAT containing the lithium energy source
used to permanently power the real time clock is
also used to retain RAM data in the absence of
VCC power through the VOUT pin.
The chip enable outputs to RAM (E1CON and
E2CON) are controlled during power transients to
prevent data corruption. The date is automatically
adjusted for months with less than 31 days and
corrects for leap years (valid until 2100). The inter-
nal watchdog timer provides programmable alarm
windows.
The nine clock bytes (Fh-9h and 1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT READ/WRITE memory
cells within the static RAM array. Clock circuitry
updates the clock bytes with current information
once per second. The information can be access-
ed by the user in the same manner as any other lo-
cation in the static memory array.
Byte 8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. Byte 7h con-
tains the watchdog timer setting. The watchdog
timer can generate either a reset or an interrupt,
depending on the state of the Watchdog Steering
Bit (WDS). Bytes 6h-2h include bits that, when
programmed, provide for clock alarm functionality.
Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.
The M48T212Y/V also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the TIMEKEEPER register data
and external SRAM, providing data security in the
midst of unpredictable system operation. As VCC
falls below VSO, the control circuitry automatically
switches to the battery, maintaining data and clock
operation until valid power is restored.
Address Decoding
The M48T212Y/V accommodates 4 address lines
(A3-A0) which allow access to the sixteen bytes of
the TIMEKEEPER clock registers. All TIMEKEEP-
ER registers reside in the SUPERVISOR chip it-
self. All TIMEKEEPER registers are accessed by
enabling E (Chip Enable).
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage
1. See Table 14., page 25 for details.
Table 3. Truth Table for SRAM Bank Select
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage
1. See Table 14., page 25 for details.
Mode
VCC
E
G
W
DQ7-DQ0
Power
Deselect
4.5V to 5.5V
or
3.0V to 3.6V
VIH
X
High-Z
Standby
WRITE
VIL
X
VIL
DIN
Active
READ
VIL
VIH
DOUT
Active
READ
VIL
VIH
High-Z
Active
Deselect
VSO to VPFD (min)
(1)
X
High-Z
CMOS Standby
Deselect
≤ VSO(1)
X
High-Z
Battery Back-Up
Mode
VCC
EX
A
E1CON
E2CON
Power
Select
4.5V to 5.5V
or
3.0V to 3.6V
Low
High
Active
Low
High
Low
Active
Deselect
High
X
High
Standby
Deselect
VSO to VPFD (min)
(1)
X
High
CMOS Standby
Deselect
≤ VSO(1)
X
High
Battery Back-Up
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