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参数资料
| 型号： | M48T212Y |
| 厂商： | 意法半导体 |
| 英文描述： | 5V/3.3V TIMEKEEPER[ CONTROLLER |
| 中文描述： | 5V/3.3V计时[控制器 |
| 文件页数： | 2/23页 |
| 文件大小： | 150K |
| 代理商： | M48T212Y |
M48T212Y, M48T212V
2/23
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubesor in
Tape & Reel form. For the 44 lead SOIC, the bat-
tery/crystal package (i.e. SNAPHAT) part number
is ”M4TXX-BR12SH” (see Table 15).
Caution:
Donot place theSNAPHAT battery/crys-
tal topin conductive foam, as this will drain the lith-
ium button-cell battery.
Automatic backup and write protection for an ex-
ternal SRAM is provided through V
OUT
, E1
CON
and E2
CON
pins. (Users are urged to insure that
voltage specifications, for both the controller chip
and external SRAM chosen, are similar). The
SNAPHAT containing the lithium energy source
used to permanently power the real time clock is
also used to retain RAM data in the absence of
V
CC
power through the V
OUT
pin.
The chip enable outputs to RAM (E1
CON
and
E2
CON
) are controlled during power transients to
prevent data corruption. The date is automatically
adjusted for months with less than 31 days and
corrects for leapyears. The internal watchdog tim-
er provides programmable alarm windows.
The nine clock bytes (Fh - 9h and 1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT
TM
read/write memory cells
within the static RAM array. Clock circuitry up-
dates theclock bytes with current information once
per second. The information can be accessed by
the user in the same manner as any other location
in the static memory array.
Byte 8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. Byte 7h con-
tains the watchdog timer setting. The watchdog
timer can generate either a reset or an interrupt,
depending on the state of the Watchdog Steering
bit (WDS).Bytes 6h-2hinclude bits that,when pro-
grammed, provide for clock alarm functionality.
Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.
Table 1. Signal Names
A0-A3
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
RSTIN1
Reset 1 Input
RSTIN2
Reset 2 Input
RST
Reset Output (Open Drain)
WDI
Watchdog Input
A
Bank Select Input
E
Chip Enable Input
EX
External Chip Enable Input
G
Output Enable Input
W
Write Enable Input
E1
CON
RAM Chip Enable 1 Output
E2
CON
RAM Chip Enable 2 Output
IRQ/FT
Int/Freq Test Output (Open Drain)
Vccsw
V
CC
Switch Output
V
OUT
Supply Voltage Output
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected internally
Figure 2. SOIC Connections
AI03020
22
44
43
42
41
VSS
1
2
3
4
A0
NC
NC
NC
NC
NC
A1
A
NC
NC
NC
NC
G
W
E1CON
DQ7
DQ6
VOUT
VCCSW
IRQ/FT
E
VCC
M48T212Y
M48T212V
10
11
12
13
14
15
16
17
18
19
20
5
6
7
8
9
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
EX
NC
WDI
E2CON
DQ0
DQ1
DQ2
DQ5
DQ4
DQ3
NC
A2
A3
RSTIN2
RST
NC
NC
NC
RSTIN1
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| M48T212Y-85MH1 | Shielded Multiconductor Cable; Number of Conductors:6; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Conductor Material:Copper; Temperature Max:80 C RoHS Compliant: Yes |
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