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参数资料
型号： M4A5-96/48-10VNC
厂商： Lattice Semiconductor Corporation
文件页数： 29/62页
文件大小： 0K
描述： IC CPLD 96MACRO 100TQFP
标准包装： 450
系列： ispMACH® 4A
可编程类型： 系统内可编程
最大延迟时间 tpd(1)： 10.0ns
电压电源 - 内部： 4.75 V ~ 5.25 V
宏单元数： 64
输入/输出数： 48
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 100-LQFP
供应商设备封装： 100-TQFP（14x14）
包装： 托盘
其它名称： 220-1853
M4A5-96/48-10VNC-ND
ispMACH 4A Family
35
BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256
Central
Switch
Matrix
Block B
CLK0–CLK3
Block A
Block OX
Block PX
Block C
Block F
Block D
Block E
Block NX
Block KX
Block MX
Block LX
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
OE
8
16
8
4
16
24
8
16
36
4
8
24
36
4
8
16
4
16
OE
8
24
36
4
8
16
4
16
OE
4
8
36
24
16
8
16
8
4
16
OE
4
36
24
16
8
16
4
8
OE
4
36
24
16
8
16
4
8
4
8
36
24
16
8
16
8
4
16
OE
8
16
8
4
16
24
8
16
36
4
OE
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
OE
8
16
8
4
16
24
8
16
36
4
8
24
36
4
8
16
4
16
OE
8
24
36
4
8
16
4
16
OE
4
8
36
24
16
8
16
8
4
16
OE
4
36
24
16
8
16
4
8
OE
4
36
24
16
8
16
4
8
4
8
36
24
16
8
16
8
4
16
OE
8
16
8
4
16
24
8
16
36
4
OE
Block G
Block J
Block H
Block I
Block JX
Block GX
Block IX
Block HX
Block K
Block N
Block L
Block M
Block FX
Block CX
Block EX
Block DX
Detail A
Repeat Detail A
Block P
Block O
Block AX
Block BX
4
17466G-068
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