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| 型号： | M4A5-96/48-7VC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 7.5 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 5/62页 |
| 文件大小： | 1078K |
| 代理商： | M4A5-96/48-7VC |
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ispMACH 4A Family
13
A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing
flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization.
It can be selected to control reset or preset.
Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization
functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data to the output switch
matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired.
The input switch matrix can send the signal back to the central switch matrix as feedback.
Note:
1. Transparent latch is unaffected by AR, AP
Table 9. Asynchronous Reset/Preset Operation
AR
AP
CLK/LE1
Q+
0
X
See Table 8
01X1
10X0
11X0
Power-Up
Reset
AP
D/L/T
AR
Q
Individual
Reset
Product Term
a. Reset
Power-Up
Preset
AP
D/L/T
AR
Q
Individual
Preset
Product Term
b. Preset
17466G-014
17466G-015
Figure 8. Asynchronous Mode Initialization Congurations
相关PDF资料 |
PDF描述 |
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| M4A5-96/48-7VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-128/64-12VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-128/64-12YI | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-128/64-55CAC | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-128/64-55VC | High Performance E 2 CMOS In-System Programmable Logic |
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