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| 型号： | M4A5-96/48-7VC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 7.5 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 60/62页 |
| 文件大小： | 1078K |
| 代理商： | M4A5-96/48-7VC |
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ispMACH 4A Family
7
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic being
implemented. The inputs to the AND gates come from the central switch matrix (Table 5), and are provided
in both true and complement forms for efficient logic implementation.
Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” The
availability and distribution of product term clusters are automatically considered by the software as it fits
functions within a PAL block. The size of a product term cluster has been optimized to provide high
utilization of product terms, making complex functions using many product terms possible. Yet when few
product terms are used, there will be a minimal number of unused—or wasted—product terms left over.
The product term clusters available to each macrocell within a PAL block are shown in Tables 6 and 7.
Each product term cluster is associated with a macrocell. The size of a cluster depends on the configuration
of the associated macrocell. When the macrocell is used in synchronous mode
(Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in asynchronous
mode (Figure 2b), the cluster has 2 product terms. Note that if the product term cluster is routed to a
different macrocell, the allocator configuration is not determined by the mode of the macrocell actually
being driven. The configuration is always set by the mode of the macrocell that the cluster will drive if not
routed away, regardless of the actual routing.
In addition, there is an extra product term that can either join the basic cluster to give an extended cluster,
or drive the second input of an exclusive-OR gate in the signal path. If included with the basic cluster, this
provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term
clusters. A similar asynchronous function can have up to 18 product terms.
When the extra product term is used to extend the cluster, the value of the second XOR input can be
programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic allocator are
Table 5. PAL Block Inputs
Device
Number of Inputs to PAL Block
M4A3-32/32 and M4A5-32/32
M4A3-64/32 and M4A5-64/32
M4A3-64/64
M4A3-96/48 and M4A5-96/48
M4A3-128/64 and M4A5-128/64
33
M4A3-192/96 and M4A5-192/96
M4A3-256/128 and M4A5-256/128
34
M4A3-256/160 and M4A3-256/192
M4A3-384
M4A3-512
36
相关PDF资料 |
PDF描述 |
|---|---|
| M4A5-96/48-7VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-128/64-12VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-128/64-12YI | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-128/64-55CAC | High Performance E 2 CMOS In-System Programmable Logic |
| M4A3-128/64-55VC | High Performance E 2 CMOS In-System Programmable Logic |
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