- 您现在的位置：买卖IC网 > PDF目录180222 > M5-384/192-10AI (LATTICE SEMICONDUCTOR CORP) Fifth Generation MACH Architecture PDF资料下载
参数资料
| 型号： | M5-384/192-10AI |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 10 ns, PBGA256 |
| 封装： | BGA-256 |
| 文件页数： | 1/47页 |
| 文件大小： | 1145K |
| 代理商： | M5-384/192-10AI |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页
Publication# 20446
Rev: I
Amendment/0
Issue Date: September 2000
MACH 5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
x
High logic densities and I/Os for increased logic integration
— 128 to 512 macrocell densities
— 68 to 256 I/Os
x
Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
x
Performance features to t system needs
— 5.5 ns tPD Commercial, 7.5 ns tPD Industrial
— 182 MHz fCNT
— Four programmable power/speed settings per block
x
Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
x
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
x
Advanced E2CMOS process provides high performance, cost effective solutions
x
Supported by ispDesignEXPERT software for rapid logic development
— Supports HDL design methodologies with results optimized for MACH 5 devices
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
x
Lattice and Third-party hardware programming support
— LatticePRO software for in-system programmability support on PCs and Automated Test
Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
相关PDF资料 |
PDF描述 |
|---|---|
| M5-384/192-12AC | Fifth Generation MACH Architecture |
| M5-384/192-15AC | Fifth Generation MACH Architecture |
| M5-384/192-15AI | Fifth Generation MACH Architecture |
| M5-384/192-7AC | Fifth Generation MACH Architecture |
| M5-384/192-7AI | Fifth Generation MACH Architecture |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M5386 | 制造商:Tamura Corporation of America 功能描述: |
| M-538CT | 制造商:NEC 制造商全称:NEC 功能描述:DC Line Fileters |
| M539 | 制造商:MA-COM 制造商全称:M/A-COM Technology Solutions, Inc. 功能描述:Drivers for GaAs FET MMIC Switches and Digital Attenuators |
| M5390 NC001 | 制造商:Alpha Wire Company 功能描述:CBL 2COND 18AWG NC 1000' |
| M5390 NC002 | 制造商:Alpha Wire Company 功能描述:CBL 2COND 18AWG NC 500' |
发布紧急采购，3分钟左右您将得到回复。