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参数资料
型号： M5-512/120-20HI
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： PLD
英文描述： Fifth Generation MACH Architecture
中文描述： EE PLD, 20 ns, PQFP160
封装： HEAT SINK, PLASTIC, QFP-160
文件页数： 11/47页
文件大小： 1145K
代理商： M5-512/120-20HI
MACH 5 Family
19
BLOCK DIAGRAM — M5(LV)-512/XXX
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Block
A/Macrocells
0-15
Block
D/Macrocells
0-15
Block
B/Macrocells
0-15
Block
C/Macrocells
0-15
Block
Interconnect
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Block
A/Macrocells
0-15
Block
D/Macrocells
0-15
Block
B/Macrocells
0-15
Block
C/Macrocells
0-15
Block
Interconnect
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Block
A/Macrocells
0-15
Block
D/Macrocells
0-15
Block
B/Macrocells
0-15
Block
C/Macrocells
0-15
Block
Interconnect
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Block
A/Macrocells
0-15
Block
D/Macrocells
0-15
Block
B/Macrocells
0-15
Block
C/Macrocells
0-15
Block
Interconnect
S
E
G
M
E
N
T
CLK0
CLK1
CLK2
CLK3
4
SEGMENT
0
SEGMENT
7
SEGMENT
2
SEGMENT
1
I 0
I 1
20446G-012
Continued
相关PDF资料
PDF描述
M5LV-384/192-10AC Fifth Generation MACH Architecture
M5LV-384/192-10AI Fifth Generation MACH Architecture
M5LV-384/192-12AC Fifth Generation MACH Architecture
M5LV-384/192-12AI Fifth Generation MACH Architecture
M5LV-384/192-15AC Fifth Generation MACH Architecture
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