参数资料
型号: M5-512/120-20HI
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
英文描述: Fifth Generation MACH Architecture
中文描述: EE PLD, 20 ns, PQFP160
封装: HEAT SINK, PLASTIC, QFP-160
文件页数: 17/47页
文件大小: 1145K
代理商: M5-512/120-20HI
24
MACH 5 Family
Power Delays:
tPL1
Power level 1 delay (Note 2)
4.0
(5.0)
4.0
(5.0)
4.0
(5.0)
4.0
(5.0)
4.0
(5.0)
4.0
(5.0)
ns
tPL2
Power level 2 delay (Note 2)
6.0
(9.0)
6.0
(9.0)
6.0
(9.0)
6.0
(9.0)
6.0
(9.0)
6.0
(9.0)
ns
tPL3
Power level 3 delay (Note 2)
9.0
(17.5)
9.0
(17.5)
9.0
(17.5)
9.0
(17.5)
9.0
(17.5)
9.0
(17.5)
ns
Additional Cluster Delay:
tPT
Product term cluster delay
0.3
ns
Interconnect Delays:
tBLK
Block interconnect delay
1.5
2.0
ns
tSEG
Segment interconnect delay
4.5
5.0
6.0
ns
Reset and Preset Delays:
tSRi
Asynchronous reset or preset to internal
register output
6.0
8.0
10.0
12.0
14.0
16.0
ns
tSR
Asynchronous reset or preset to register
output
8.0
10.0
12.0
14.0
16.0
18.0
ns
tSRR
Reset and set register recovery time
5.5
7.5
8.0
9.0
10.0
11.0
ns
tSRW
Asynchronous reset or preset width
3.0
4.0
5.0
6.0
7.0
8.0
ns
Clock Enable Delays:
tCES
Clock enable setup time
4.0
5.0
6.0
7.0
8.0
ns
tCEH
Clock enable hold time
3.0
4.0
5.0
6.0
7.0
ns
Width:
tWLS
Global clock width low (Note 3)
2.5
3.0
4.0
5.0
6.0
ns
tWHS
Global clock width high (Note 3)
2.5
3.0
4.0
5.0
6.0
ns
tWLA
Product term clock width low
3.0
4.0
5.0
6.0
7.0
8.0
ns
tWHA
Product term clock width high
3.0
4.0
5.0
6.0
7.0
8.0
ns
tGWA
Gate width low (for low transparent) or
high (for high transparent)
3.0
4.0
5.0
6.0
7.0
8.0
ns
tWIR
Input register clock width low or high
3.0
4.0
5.0
6.0
7.0
8.0
ns
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-6
-7
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
相关PDF资料
PDF描述
M5LV-384/192-10AC Fifth Generation MACH Architecture
M5LV-384/192-10AI Fifth Generation MACH Architecture
M5LV-384/192-12AC Fifth Generation MACH Architecture
M5LV-384/192-12AI Fifth Generation MACH Architecture
M5LV-384/192-15AC Fifth Generation MACH Architecture
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