参数资料
型号: M5-512/256-7SAI
厂商: Lattice Semiconductor Corporation
文件页数: 6/42页
文件大小: 0K
描述: IC CPLD ISP 512MC 256IO 352SBGA
标准包装: 24
系列: MACH® 5
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 7.5ns
电压电源 - 内部: 4.5 V ~ 5.5 V
宏单元数: 512
输入/输出数: 256
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 352-LBGA
供应商设备封装: 352-SBGA(35x35)
包装: 托盘
14
MACH 5 Family
BLOCK DIAGRAM — M5(LV)-128/XXX
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Block A/Macrocells 0-15
Block D/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block Interconnect
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Block A/Macrocells 0-15
Block D/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block Interconnect
S E G M E N T I N T E R C O N N E C T
CLK0
CLK1
CLK2
CLK3
4
SEGMENT 0
SEGMENT 1
I0, 1
I2, 3
2
20446G-007
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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