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参数资料
| 型号： | M54HC691 |
| 厂商： | 意法半导体 |
| 元件分类： | 通用总线功能 |
| 英文描述： | Binary Up/Down Counter/Register(二进制计数器/寄存器) |
| 中文描述： | 二进制加/减计数器/寄存器（二进制计数器/寄存器） |
| 文件页数： | 15/23页 |
| 文件大小： | 433K |
| 代理商： | M54HC691 |
Symbol
Parameter
Test Conditions
Value
-40 to 85
o
C
74HC
Min.
3.6
18
21
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25
o
C
54HC and 74HC
Min.
Typ.
4.4
12
22
45
26
53
48
15
13
61
19
17
32
15
13
28
-55 to 125
o
C
54HC
Min.
3
15
18
Max.
Max.
Max.
f
MAX
Maximum Clock
Frequency
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
50
MHz
t
PZL
t
PZH
Output Enable
Time
50
R
L
= 1 K
120
24
20
150
30
26
145
29
25
75
15
13
75
15
13
150
30
26
190
38
32
180
36
31
95
19
16
95
19
16
180
36
31
225
45
38
220
44
37
110
22
19
110
22
19
ns
150
R
L
= 1 K
ns
t
PLH
t
PHL
Output Disable
Time
50
R
L
= 1 K
ns
t
W(H)
t
W(L)
Minimum Pulse
Width
(CCK - RCK)
50
ns
7
6
t
W(L)
Minimum Pulse
Width
(CCLR - RCLR)
(for HC690/691)
50
40
8
7
ns
t
s
Minimum Set-up
Time (LOAD,
ENT, ENP)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
50
68
17
14
44
11
9
44
11
9
150
30
26
100
20
17
100
20
17
190
38
32
125
25
21
125
25
21
220
44
37
145
29
25
145
29
25
ns
t
s
Minimum Set-up
Time
(A, B, C, D)
50
ns
t
s
Minimum Set-up
Time
(CCLR, RCLR)
(for HC692/693)
50
ns
t
s
Minimum Set-up
Time
(CCK, RCK)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
50
48
12
10
125
25
21
0
0
0
25
5
5
10
155
31
26
0
0
0
30
6
5
10
180
36
31
0
0
0
40
8
7
10
ns
t
h
Minimum Hold
Time
50
ns
t
REM
Minimum
Removal Time
(for HC690/691)
50
ns
C
IN
Input Capacitance
Power Dissipation
Capacitance
5
pF
C
PD
(*)
for HC690/691
for HC692/693
70
80
pF
(*) C
PD
isdefined asthe value ofthe IC’sinternal equivalent capactance which is calculated from the operating current consumption without load.
(Refer to Test Circuit).Average operting current can be obtained by thefollowingequation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
AC ELECTRICAL CHARACTERISTICS
(Continued)
M54/M74HC690/691/692/693
15/23
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