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参数资料
| 型号： | M66004SP |
| 元件分类： | 显示控制器 |
| 英文描述： | 36 X 16 DOTS FLUORESCENT DSPL CTRL, PDIP64 |
| 封装： | PLASTIC, DIP-64 |
| 文件页数： | 2/15页 |
| 文件大小： | 3009K |
| 代理商： | M66004SP |
M66238FP
REJ03F0268-0200 Rev.2.00 Mar 18, 2008
Page 10 of 14
1.2 Setting of Trigger Edge when D1 = 1
One-shot pulse start timing:
1st leading edge of CKO after TR rise
(except the rise of a spike which occurs when CKO is stopped).
One-shot pulse polarity:
Negative pulse
One-shot pulse width:
16 cycles of CKO
CKO output dividing ratio:
1/2 division
An example set for the condition of address (A1, A0) = (1, 0), data (D6, D5, D4, D3, D2, D1, D0) = (0, 1, 1, 0, 0, 1, 0)
is shown below. CKO is a clock output synchronized by TR and PULSE is a one-shot pulse synchronized with the rise
of CKO.
Internal VCO
oscillator clock
tp = 1 / fvco
tp = 1 / fout
tlp
tw (TR)
tsp (CKO)
tss (CKO)
tw (PULSE)
SPIKE
t
TR
CKO
PULSE
2. Sync Clock Spike Removal Mode upon Occurrence of Trigger
When address (A1, A0) = (1, 0) and data (D6, D5, D4, D3, D2, D1, D0) = (0, 1, 1, 0, 1, 0, 0), CKO with the first rise
after occurrence of a trigger is output and then CKO stops.
However, this mode is not available when D1 = 1 in trigger edge setting. Set a wide TR so that TR sync edge is entered
200 ns or more after CKO stops.
TR
tw (TR)
200 ns or more required
1st
tss (CKO)
tss (CKOB)
tss (PULSE)
tw (PULSE)
t
CKO
CKOB
PULSE
Notes: 1. 200 ns or more required
2. tss (CKO, CKOB, PULSE) is defined by input clock width "L" +
α. In addition, the value of α denotes IC
internal delay, and the values of
α and tss are definite unless temperature, Vcc, etc. are changed, and tss
variations at that time is defined as
t (sync accuracy: jitter).
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