参数资料
型号: M68AW127BM70N6T
厂商: 意法半导体
英文描述: 1Mbit 128K x8, 3.0V Asynchronous SRAM
中文描述: 1Mbit的128K的× 8,3.0V异步SRAM
文件页数: 13/20页
文件大小: 327K
代理商: M68AW127BM70N6T
13/20
M68AW127B
Table 8. Write Mode AC Characteristics
Note: 1. At any given temperature and voltage condition, t
WLQZ
is less than t
WHQX
for any given device.
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
Symbol
Parameter
M68AW127B
Unit
70
100
t
AVAV
Write Cycle Time
Min
70
100
ns
t
AVEH
Address Valid to Chip Enable High
Min
60
80
ns
t
AVEL
Address valid to Chip Enable Low
Min
0
0
ns
t
AVWH
Address Valid to Write Enable High
Min
60
80
ns
t
AVWL
Address Valid to Write Enable Low
Min
0
0
ns
t
DVEH
Input Valid to Chip Enable High
Min
30
40
ns
t
DVWH
Input Valid to Write Enable High
Min
30
40
ns
t
EHAX
Chip Enable High to Address Transition
Min
0
0
ns
t
EHDX
Chip enable High to Input Transition
Min
0
0
ns
t
ELEH
Chip Enable Low to Chip Enable High
Min
60
80
ns
t
ELWH
Chip Enable Low to Write Enable High
Min
60
80
ns
t
WHAX
Write Enable High to Address Transition
Min
0
0
ns
t
WHDX
Write Enable High to Input Transition
Min
0
0
ns
t
WHQX (1)
Write Enable High to Output Transition
Min
5
5
ns
t
WLEH
Write Enable Low to Chip Enable High
Min
60
70
ns
t
WLQZ (1,2)
Write Enable Low to Output Hi-Z
Max
20
30
ns
t
WLWH
Write Enable Low to Write Enable High
Min
60
70
ns
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